公开(公告)号：WO1997032340A1

公开(公告)日：1997-09-04

申请号：PCT/US1997002880

申请日：1997-02-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  GONZALEZ, Fernando ,  LOWREY, Tyler, A. ,  DOAN, Trung, Tri ,  TURI, Raymond, A. ,  WOLSTENHOLME, Graham, R.

IPC: H01L21/285

CPC classification number: H01L29/66136 ,  H01L27/0814 ,  H01L29/861 ,  Y10S257/91 ,  Y10S438/979

Abstract: A vertical diode is provided having a diode opening (24) extending through an insulation layer (20) and contacting an active region (18) on a silicon wafer (12). A titanium silicide layer (66) covers the interior surface (65) of the diode opening (24) and contacts the active region (18). The diode opening (24) is initially filled with an amorphous silicon plug (38) that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug (38) has a top portion (42) that is heavily doped with a first type dopant and a bottom portion (44) that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer (66). For one embodiment of the vertical diode, a programmable resistor contacts the top portion (42) of the silicon plug (38) and a metal line (48) contacts the programmable resistor.

Abstract translation: 提供了具有延伸穿过绝缘层（20）并接触硅晶片（12）上的有源区（18）的二极管开口（24）的垂直二极管。 钛硅化物层（66）覆盖二极管开口（24）的内表面（65）并接触有源区（18）。 二极管开口（24）最初填充有非晶硅塞（38），其在沉积期间被掺杂，随后被重结晶以形成大晶粒多晶硅。 硅插头（38）具有重掺杂有第一类型掺杂剂的顶部部分（42）和轻掺杂有第二类型掺杂剂的底部部分（44）。 顶部由底部界定，以便不与硅化钛层（66）接触。 对于垂直二极管的一个实施例，可编程电阻器接触硅插头（38）的顶部（42）并且金属线（48）接触可编程电阻器。

公开(公告)号：WO1997025743A1

公开(公告)日：1997-07-17

申请号：PCT/US1997000168

申请日：1997-01-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  SEYYEDY, Mirmajid ,  MA, Manny, K., F.

IPC: H01L23/525

CPC classification number: G11C17/16 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit laser antifuse is described which has two physical states. In the first physical state the laser antifuse has two conductive plates electrically separated by a layer of dielectric material. In the second physical state the two conductive plates are electrically connected through the dielectric in response to an external radiation source, such as a laser.

Abstract translation: 描述了具有两种物理状态的集成电路激光反熔丝。 在第一物理状态下，激光反熔丝具有由介电材料层电隔离的两个导电板。 在第二物理状态下，响应于诸如激光器的外部辐射源，两个导电板通过电介质电连接。

公开(公告)号：WO1997015012A1

公开(公告)日：1997-04-24

申请号：PCT/US1996016708

申请日：1996-10-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  WALTHER, Terry, R.

IPC: G06F13/40

CPC classification number: G06F13/4072

Abstract: A memory bus termination module is described for reducing overshoot and undershoot in a communication bus. The module includes circuitry which reduces or eliminates unwanted signal fluctuations. The module can be placed in a personal computer memory bus to allow the computer purchaser to expand memory capabilities, and in particular install high data rate memories. These memories include burst access memories which operate at or above 66 MHz. Two clamping diodes are provided in the termination circuitry and connected to communication lines of the bus.

Abstract translation: 描述了用于减少通信总线中的过冲和下冲的存储器总线终端模块。 该模块包括减少或消除不需要的信号波动的电路。 该模块可以放置在个人计算机存储器总线中，以允许计算机购买者扩展存储器能力，并且特别地安装高数据速率存储器。 这些存储器包括在66MHz以上工作的突发存取存储器。 在终端电路中提供两个钳位二极管，并连接到总线的通信线路。

公开(公告)号：WO1997011493A1

公开(公告)日：1997-03-27

申请号：PCT/US1996001164

申请日：1996-01-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  KEETH, Brent ,  FAZAN, Pierre, C.

IPC: H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10811

Abstract: Processes are disclosed which facilitate improved high density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes, i) a total of no more than 68,000,000 functional and operably addressable memory cells (160) arranged in multiple memory arrays formed on a semiconductor die (12); and ii) circuitry (166) formed on the semiconductor die permitting data to be written to an read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells. More preferably, there is at least 100 square microns of continous die surface area having at least 170 of the functional and operably addressable memory cells.

Abstract translation: 公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。 半导体存储器件包括：i）布置在形成在半导体管芯（12）上的多个存储器阵列中的总共不超过68,000,000个功能和可操作地址的存储器单元（160）; 以及ii）形成在所述半导体管芯上的电路（166），允许将数据写入到从所述存储器单元中的一个或多个读取的存储器阵列中，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域， 128个功能和可操作地寻址的存储单元。 更优选地，存在具有至少170个功能和可操作地寻址的存储器单元的至少100平方微米的连续管芯表面区域。

公开(公告)号：WO1997008701A1

公开(公告)日：1997-03-06

申请号：PCT/US1996013711

申请日：1996-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MERRITT, Todd ,  MANNING, Troy

IPC: G11C07/00

CPC classification number: G11C7/1045

Abstract: A memory circuit is described which can operate in one of a number of operating modes. The operating mode of the memory circuit can be changed in a non-volatile manner after the memory circuit is packaged to reduce production scrap or meet market demands. Disable circuitry is described which includes an anti-fuse that can be externally selectively blown to disable an operating mode. Control circuitry included in the memory circuit enables a new operating mode after the first operating mode is disabled. A method of selectively disabling an operating mode is described. A hierarchical scheme is also desdribed for enabling a new operating mode from a group of operating modes, for example page-mode, extended data output (EDO), or burst EDO.

Abstract translation: 描述了可以以多种操作模式之一操作的存储器电路。 在存储电路封装之后，可以以非易失性的方式改变存储电路的工作模式以减少生产废料或满足市场需求。 描述了禁止电路，其包括可以从外部选择性地吹制以禁用操作模式的反熔丝。 包含在存储器电路中的控制电路在禁用第一操作模式之后启用新的操作模式。 描述了选择性地禁用操作模式的方法。 还描述了一种分层方案，用于从一组操作模式启用新的操作模式，例如页面模式，扩展数据输出（EDO）或突发EDO。

公开(公告)号：WO1997003401A1

公开(公告)日：1997-01-30

申请号：PCT/US1996010547

申请日：1996-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MORGAN, Donald, M.

IPC: G06F11/20

CPC classification number: G11C29/787

Abstract: An integrated circuit includes primary circuit elements selectable by n address bits. A master storage device is programmable to indicate that at least one primary circuit element is being replaced. Redundant circuit elements each include a non-precharging matching circuit, which includes sub-match circuits. The sub-match circuits include two state storage devices corresponding to one of the possible binary values of at least one of the n address bits and activate a sub-match signal when the binary value of the at least one of the n address bits corresponds to one of the two state storage devices in a first state if the master storage device is programmed. A match circuit activates a match signal in response to all sub-match signals being active to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits.

Abstract translation: 集成电路包括可由n个地址位选择的主电路元件。 主存储装置可编程以指示至少一个主要电路元件正在被更换。 冗余电路元件各自包括非预充电匹配电路，其包括子匹配电路。 子匹配电路包括对应于n个地址位中的至少一个的可能二进制值之一的两个状态存储设备，并且当n个地址位中的至少一个的二进制值对应于 如果主存储设备被编程，则处于第一状态的两个状态存储设备中的一个。 匹配电路响应于所有子匹配信号有效以激活匹配信号，以禁止主电路元件被n个地址位的对应二进制值选择，并且使冗余电路元件能够被对应的二进制 n个地址位的值。

公开(公告)号：WO1996039699A1

公开(公告)日：1996-12-12

申请号：PCT/US1996009073

申请日：1996-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  SEYYEDY, Mirmajid ,  CASPER, Stephen, L.

IPC: G11C11/409

CPC classification number: G11C7/067 ,  G11C11/4091

Abstract: An integrated circuit dynamic memory device is described which stores data in memory cells as a charge on a capacitor. The memory cells can be selectively connected to a digit line. Sensing circuitry, including both p-sense and n-sense amplifiers, is connected to the digit line for sensing data stored in the memory cells. Equalization circuitry is described to equalize the sense amplifiers by connecting both nodes of the sense amplifiers to the digit line prior to sensing data stored on the memory cell.

Abstract translation: 描述了将存储器单元中的数据作为电容器上的电荷存储的集成电路动态存储器件。 存储单元可以选择性地连接到数字线。 感测电路，包括p感测放大器和n-sense放大器，连接到数字线路，用于感测存储在存储器单元中的数据。 描述均衡电路以在感测存储在存储单元上的数据之前将读出放大器的两个节点连接到数字线来均衡读出放大器。

公开(公告)号：WO1996035234A1

公开(公告)日：1996-11-07

申请号：PCT/US1996003421

申请日：1996-03-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  THOMPSON, J., Wayne ,  MANNING, Troy, A.

IPC: H01L27/108

CPC classification number: H01L27/108

Abstract: Integrated circuitry includes, a) a first array of electronic devices (32) comprising a series of conductive runners (33) extending outwardly of the memory array with adjacent runners having a device pitch of 0.6 micron or less in a pitch direction, b) a second array of electronic devices (43) peripheral to the first array, the 0.6 pitch conductive runners of the first array extending into the second array, at least some of the conductive runners of the series having respective disjointed gaps (82) therewithin within the second array, the gaps being aligned with one another in the second array, c) a cross running conductor (90-97) extending substantially parallel with the pitch direction and over the aligned gaps within the second array, d) an insulating dielectric layer provided relative to the disjointed gaps within the second array; and e) a series of electrically conductive plugs (105-112) provided within the insulating dielectric layer and running substantially perpendicular to the pitch direction within the second array, the conductive plugs respectively extending across the respective gaps between and electrically interconnecting the respective disjointed conductive runners within the second array, the cross running conductor extending elevationally over the conductive plugs. Memory integrated circuitry is also disclosed which incorporates electrically conductive plugs (47, 50, 52) which electrically interconnect disjointed active area regions (431, 421, 411, 401, 391) of different transistors in pitch cells.

Abstract translation: 集成电路包括：a）电子器件（32）的第一阵列，其包括从存储器阵列向外延伸的一系列导电流道（33），相邻的流道在俯仰方向上具有0.6微米或更小的器件间距，b） 第二阵列的第二阵列的电子器件（43），第一阵列的0.6节距导电流道延伸到第二阵列中，该系列的至少一些导电流道在其内部具有相应的不相交的间隙（82） 阵列，所述间隙在所述第二阵列中彼此对准，c）跨越所述俯仰方向延伸并跨越所述第二阵列内的所述对准的间隙的交叉运行导体（90-97），d）相对于所述第二阵列提供的绝缘介电层 到第二阵列中的不相交的间隙; 以及e）一系列导电插头（105-112），其设置在所述绝缘介电层内并且基本上垂直于所述第二阵列内的所述俯仰方向运行，所述导电插塞分别延伸穿过相应的间隙并将相应的不相交的导电 在第二阵列内的横梁，横向运行的导体在导电插头上垂直延伸。 还公开了一种存储器集成电路，其包括导电插头（47,50,52），其将间距单元中的不同晶体管的不相交的有源区域（431,421,411,401,391）电连接。

公开(公告)号：WO1996032728A1

公开(公告)日：1996-10-17

申请号：PCT/US1996003382

申请日：1996-03-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MARR, Kenneth, W.

IPC: G11C29/00

CPC classification number: G11C29/46 ,  G11C11/41 ,  G11C29/50 ,  G11C2029/5004

Abstract: A circuit and method provide isolated modulation of SRAM bitline voltage levels for improved voltage bump retention testing of the SRAM cells. A first FET is connected to Vcc, bitline load gates of the SRAM cell, and test mode operation control logic. A second FET is connected to the bitline load gates, the test mode logic, and an external pin of the SRAM device. During test mode operation, the first FET disables Vcc to the bitlines, and the second FET enables the internal bitline voltage levels to be modulated by a voltage supply received through the external pin of the device. Modulation of the bitline voltage levels is isolated from normal operating voltage levels of peripheral circuitry such as the wordlines. An alternate embodiment provides a CMOS transmission gate in place of the second FET.

Abstract translation: 电路和方法提供SRAM位线电压电平的隔离调制，以改进SRAM单元的电压突起保持测试。 第一FET连接到Vcc，SRAM单元的位线负载门和测试模式操作控制逻辑。 第二个FET连接到位线负载门，测试模式逻辑和SRAM器件的外部引脚。 在测试模式操作期间，第一个FET将Vcc禁止位线，而第二个FET使得内部位线电压电平可以通过器件的外部引脚接收的电压来调制。 位线电压电平的调制与诸如字线的外围电路的正常工作电压电平隔离。 替代实施例提供了一个CMOS传输门来代替第二个FET。

公开(公告)号：WO1996030937A1

公开(公告)日：1996-10-03

申请号：PCT/US1996004086

申请日：1996-03-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  LAKE, Rickie, Charles

IPC: H01L21/288

CPC classification number: H01L24/81 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/27 ,  H01L24/28 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75315 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  Y10T29/41 ,  H01L2924/00

Abstract: A method and apparatus for mounting a component, such as a semiconductor die (14), to a substrate (10) are provided. A z-axis anisotropic adhesive (12) is applied to the substrate (10) and the component is placed on the anisotropic adhesive (12). During a curing process a cover film (30) is drawn over the component and substrate (10) to maintain the anisotropic adhesive (12) in compression. A conveyorized curing apparatus includes a conveyor belt (26) for moving the substrate (10) through a heated process chamber (22). The cover film (30) is mounted on an endless belt and is adapted to move at a same speed as the conveyor belt. As the die (14) and substrate (10) are moved through the process chamber (22), a vacuum plenum (28) draws the cover film (30) over the die (14) and substrate (10) to exert a uniform force on the component.

Abstract translation: 提供了用于将诸如半导体管芯（14）的部件安装到衬底（10）的方法和装置。 将z轴各向异性粘合剂（12）施加到基板（10）上，并将该部件放置在各向异性粘合剂（12）上。 在固化过程中，将覆盖膜（30）拉伸到部件和基底（10）上，以使各向异性粘合剂（12）保持压缩。 传送带固化设备包括用于通过加热处理室（22）移动衬底（10）的传送带（26）。 覆盖膜（30）安装在环形带上并且适于以与传送带相同的速度移动。 当模具（14）和基底（10）移动通过处理室（22）时，真空增压室（28）将覆盖膜（30）拉伸在模具（14）和基底（10）上以施加均匀的力 在组件上。