公开(公告)号：US20140264781A1

公开(公告)日：2014-09-18

申请号：US14201247

申请日：2014-03-07

Applicant: Robert Bosch GmbH

Inventor： Ando Lars Feyh ,  Fabian Purkl ,  Andrew Graham ,  Gary Yama

IPC: H01L21/02 ,  H01L29/06

CPC classification number: B81C1/00809 ,  B81C2201/016 ,  H01L21/02601 ,  H01L23/3192 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a passivation layer and a passivation layer for an electronic device. The passivation layer includes at least one passivation film layer and at least one nanoparticle layer. A first film layer is formed of an insulating matrix, such as aluminum oxide (Al2O3) and a first layer of a noble metal nanoparticle layer, such as a platinum nanoparticle layer, is deposited on the first film layer. Additional layers are formed of alternating film layers and nanoparticle layers. The resulting passivation layer provides a thin and robust passivation layer of high film quality to protect electronic devices, components, and systems from the disruptive environmental conditions.

Abstract translation: 一种制造用于电子设备的钝化层和钝化层的方法。 钝化层包括至少一个钝化膜层和至少一个纳米颗粒层。 第一膜层由诸如氧化铝（Al2O3）的绝缘基体形成，并且第一层金属纳米颗粒层（例如铂纳米颗粒层）沉积在第一膜层上。 附加层由交替的膜层和纳米颗粒层形成。 所得到的钝化层提供了一种具有高膜质量的薄且坚固的钝化层，以保护电子设备，部件和系统免受破坏性环境条件的影响。

公开(公告)号：US08093087B2

公开(公告)日：2012-01-10

申请号：US13209461

申请日：2011-08-15

Applicant: Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Jhyy-Cheng Liou

Inventor： Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Jhyy-Cheng Liou

IPC: H01L21/00

CPC classification number: B81C1/00246 ,  B81B2203/0315 ,  B81B2207/015 ,  B81C2201/016 ,  B81C2203/0714 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00

Abstract: Method for fabricating MEMS device has a first surface and a second surface and having a MEMS region and an IC region. A MEMS structure is formed over the first surface. A structural dielectric layer is formed over the first surface. The structural dielectric layer has a dielectric member and the spaces surrounding the MEMS structure is filled with the dielectric member. The substrate is patterned by etching process from the second surface of the substrate to expose a portion of the dielectric member filled in the space surrounding the MEMS structure. A wettable thin layer is formed to cover an exposed portion of the substrate at the second surface. An etching process is performed on the dielectric member filled in the spaces surrounding the MEMS structure. The MEMS structure is exposed and released by the etching process. The etching process comprises an isotropic etching process with a wet etchant.

Abstract translation: 制造MEMS器件的方法具有第一表面和第二表面，并且具有MEMS区域和IC区域。 在第一表面上形成MEMS结构。 在第一表面上形成结构介电层。 结构介电层具有电介质构件，并且围绕MEMS结构的空间填充有电介质构件。 通过从衬底的第二表面的蚀刻工艺对衬底进行构图，以暴露在围绕MEMS结构的空间中填充的电介质构件的一部分。 形成可湿性薄层以覆盖第二表面处的基板的暴露部分。 对填充在围绕MEMS结构的空间的电介质构件进行蚀刻处理。 通过蚀刻工艺暴露和释放MEMS结构。 蚀刻工艺包括具有湿蚀刻剂的各向同性蚀刻工艺。

公开(公告)号：US20110300659A1

公开(公告)日：2011-12-08

申请号：US13209461

申请日：2011-08-15

Applicant: Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Jhyy-Cheng Liou

Inventor： Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Jhyy-Cheng Liou

IPC: H01L21/311

CPC classification number: B81C1/00246 ,  B81B2203/0315 ,  B81B2207/015 ,  B81C2201/016 ,  B81C2203/0714 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00

Abstract: Method for fabricating MEMS device has a first surface and a second surface and having a MEMS region and an IC region. A MEMS structure is formed over the first surface. A structural dielectric layer is formed over the first surface. The structural dielectric layer has a dielectric member and the spaces surrounding the MEMS structure is filled with the dielectric member. The substrate is patterned by etching process from the second surface of the substrate to expose a portion of the dielectric member filled in the space surrounding the MEMS structure. A wettable thin layer is formed to cover an exposed portion of the substrate at the second surface. An etching process is performed on the dielectric member filled in the spaces surrounding the MEMS structure. The MEMS structure is exposed and released by the etching process. The etching process comprises an isotropic etching process with a wet etchant.

Abstract translation: 制造MEMS器件的方法具有第一表面和第二表面，并且具有MEMS区域和IC区域。 在第一表面上形成MEMS结构。 在第一表面上形成结构介电层。 结构介电层具有电介质构件，并且围绕MEMS结构的空间填充有电介质构件。 通过从衬底的第二表面的蚀刻工艺对衬底进行构图，以暴露在围绕MEMS结构的空间中填充的电介质构件的一部分。 形成可湿性薄层以覆盖第二表面处的基板的暴露部分。 对填充在围绕MEMS结构的空间的电介质构件进行蚀刻处理。 通过蚀刻工艺暴露和释放MEMS结构。 蚀刻工艺包括具有湿蚀刻剂的各向同性蚀刻工艺。

公开(公告)号：US08022554B2

公开(公告)日：2011-09-20

申请号：US11763801

申请日：2007-06-15

Applicant: Pavan Gupta ,  Eric Razda

Inventor： Pavan Gupta ,  Eric Razda

IPC: H01L23/48 ,  H01L23/34

CPC classification number: B81B7/0083 ,  B81B7/007 ,  B81B7/0077 ,  B81B2201/0271 ,  B81B2207/07 ,  B81B2207/094 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00333 ,  B81C1/00341 ,  B81C2201/016 ,  B81C2203/0118 ,  B81C2203/0154 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/498 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A stacked die package for an electromechanical resonator system includes a chip that contains an electromechanical resonator bonded onto the control chip for the electromechanical resonator by a thermally and/or electrically conductive epoxy. In various embodiments, the electromechanical resonator can be a micro-electromechanical system (MEMS) resonator or a nano-electromechanical system (NEMS) resonator. Packaging configurations that may include the chip that contains the electromechanical resonator and the control chip include chip-on-lead (COL), chip-on-paddle (COP), and chip-on-tape (COT) packages. The stacked die package provides small package footprint and/or low package thickness, as well as low thermal resistance and a robust conductive path between the chip that contains the electromechanical resonator and the control chip.

Abstract translation: 用于机电谐振器系统的堆叠管芯封装包括芯片，其包含通过热和/或导电环氧树脂粘合到用于机电谐振器的控制芯片上的机电谐振器。 在各种实施例中，机电谐振器可以是微机电系统（MEMS）谐振器或纳米机电系统（NEMS）谐振器。 可以包括包含机电谐振器和控制芯片的芯片的封装结构包括芯片引线（COL），片上芯片（COP）和片上芯片（COT）封装。 堆叠管芯封装提供小的封装封装和/或低封装厚度，以及低热阻和在包含机电谐振器的芯片和控制芯片之间的坚固的导电路径。

公开(公告)号：US20060068510A1

公开(公告)日：2006-03-30

申请号：US10520886

申请日：2003-05-06

Applicant: Andrea Urban ,  Franz Laermer ,  Klaus Breitschwerdt

Inventor： Andrea Urban ,  Franz Laermer ,  Klaus Breitschwerdt

IPC: H01L21/00

CPC classification number: B81C1/00571 ,  B81B2203/033 ,  B81C2201/016 ,  H01L21/0332

Abstract: A layer system and a method for producing the layer system are provided, the layer system having a silicon layer, on which at least regionally a passivating layer is superficially deposited, the passivating layer having a first, at least largely inorganic partial layer and a second, at least largely polymer partial layer. The method includes producing on the silicon layer, a first, inorganic partial layer, and producing on this first partial layer a second, polymer partial layer, which form the passivating layer. The production of the intermediate layer occurs in such a way that the intermediate layer in its surface area adjoining the first partial layer is composed as the first partial layer, and the intermediate layer in its surface area adjoining the second partial layer is composed as the second partial layer. The composition of the intermediate layer transitions, either continuously or in steps, from the composition corresponding to the first partial layer into the composition corresponding to the second partial layer.

Abstract translation: 提供了一种用于制造层系统的层系统和方法，所述层系统具有硅层，其上至少区域地表面钝化钝化层，所述钝化层具有第一至少大部分无机部分层和第二层 ，至少主要是聚合物部分层。 该方法包括在硅层上制备第一无机部分层，并在该第一部分层上制备形成钝化层的第二聚合物部分层。 中间层的制造以与第一部分层相邻的表面区域的中间层构成为第一部分层的方式发生，并且与其邻接的第二部分层的表面区域中的中间层构成为第二部分层 部分层。 中间层的组成可以从对应于第一部分层的组合物连续地或逐步地转变成对应于第二部分层的组合物。

公开(公告)号：US06960536B2

公开(公告)日：2005-11-01

申请号：US10613459

申请日：2003-07-03

Applicant: Wilhelm Frey ,  Franz Laermer ,  Christoph Duenn

Inventor： Wilhelm Frey ,  Franz Laermer ,  Christoph Duenn

IPC: B81C1/00 ,  C23F1/14 ,  H01L21/306 ,  H01L21/461

CPC classification number: B81C1/00571 ,  B81C1/00595 ,  B81C2201/0133 ,  B81C2201/016 ,  B81C2203/0735 ,  C23F1/14 ,  H01L21/30604

Abstract: A method for producing a microsystem that has, situated on a substrate, a first functional layer that includes a conductive area and a sublayer. Situated on the first functional layer is a second mechanical functional layer, which is first initially applied onto a sacrificial layer situated and structured on the first functional layer. In addition, a layer is situated on the side of the sublayer facing away from the conductive area. The layer constitutes a protective layer on the first functional layer that acts in areas during a sacrificial layer etching process so that during removal of the sacrificial layer no etching of the areas of the first functional layer covered by the protective layer occurs, and that in the region of the areas of the first functional layer implemented without the protective layer the sublayer is removed essentially selectively to the conductive area at the same time as the sacrificial layer. Further, a method is described for producing integrated microsystems having silicon-germanium functional layers, sacrificial layers containing germanium, and open metal surfaces. The sacrificial layers containing germanium are at least partially removed in an etching solution, a pH value of the etching solution being kept at least approximately neutral during the etching procedure using a buffer.

Abstract translation: 一种微系统的制造方法，其具有位于基板上的包括导电区域和子层的第一功能层。 位于第一功能层上的是第二机械功能层，其首先被初始施加到位于第一功能层上并构成的牺牲层上。 此外，层位于子层背离导电区域的一侧。 该层在第一功能层上构成保护层，其在牺牲层蚀刻工艺期间在区域中起作用，使得在去除牺牲层期间不会发生由保护层覆盖的第一功能层的区域的蚀刻， 在没有保护层的情况下实现的第一功能层的区域的区域在与牺牲层同时基本上选择性地去除导电区域。 此外，描述了一种用于制造具有硅 - 锗功能层，包含锗的牺牲层和开放金属表面的集成微系统的方法。 在蚀刻溶液中至少部分地除去含有锗的牺牲层，在使用缓冲液的蚀刻过程中，蚀刻溶液的pH值保持至少大致为中性。

公开(公告)号：US06878567B2

公开(公告)日：2005-04-12

申请号：US09895127

申请日：2001-06-29

Applicant: Paul Winer ,  George P. Vakanas

Inventor： Paul Winer ,  George P. Vakanas

IPC: B01L3/00 ,  B81B1/00 ,  B81C1/00 ,  H01L21/00

CPC classification number: H01L21/00 ,  B01L3/5027 ,  B81B2201/058 ,  B81B2203/0338 ,  B81C1/00714 ,  B81C2201/016 ,  Y10S438/94 ,  Y10S438/958

Abstract: A method and apparatus for fabrication of passivated microfluidic structures is disclosed. The method includes providing a substrate having a microfluidic structure formed therein. The microfluidic structure is embedded by an embedding layer. The method further includes passivating the embedded microfluidic structure by locally heating the microfluidic structure surface in a reactive atmosphere, wherein the passivated microfluidic structure is suitable for transporting a fluid.

Abstract translation: 公开了一种用于制造钝化微流体结构的方法和装置。 该方法包括提供其中形成有微流体结构的基底。 微流体结构由嵌入层嵌入。 该方法还包括通过在反应性气氛中局部加热微流体结构表面来钝化嵌入的微流体结构，其中钝化的微流体结构适于输送流体。

公开(公告)号：US06693045B2

公开(公告)日：2004-02-17

申请号：US09683692

申请日：2002-02-04

Applicant: Tsung-Ping Hsu ,  In-Yao Lee ,  Hung-Sheng Hu ,  Chung-Cheng Chou ,  Wei-Lin Chen

Inventor： Tsung-Ping Hsu ,  In-Yao Lee ,  Hung-Sheng Hu ,  Chung-Cheng Chou ,  Wei-Lin Chen

IPC: H01L2100

CPC classification number: B81C1/00626 ,  B81C2201/0133 ,  B81C2201/016

Abstract: A gradational etching method for high density wafer production. The gradational etching method acts on a substrate having a first passivation layer and a second passivation layer on a top surface and a bottom surface, respectively, of the substrate. A first etching process is performed to simultaneously etch the substrate and the first passivation layer to remove the first passivation layer. Finally, a second etching process is performed to etch the substrate to a designated depth that is used to control the thickness of the wafer after the second etching process.

Abstract translation: 用于高密度晶片生产的渐变蚀刻方法。 分级蚀刻方法分别作用于具有基板的顶表面和底表面上的第一钝化层和第二钝化层的基板上。 执行第一蚀刻工艺以同时蚀刻衬底和第一钝化层以去除第一钝化层。 最后，执行第二蚀刻工艺以将衬底蚀刻到用于在第二蚀刻工艺之后控制晶片的厚度的指定深度。

公开(公告)号：US20040018734A1

公开(公告)日：2004-01-29

申请号：US10202331

申请日：2002-07-24

Applicant: LOCKHEED MARTIN CORPORATION

Inventor： James H. Schermerhorn ,  Matthew C. Nielsen ,  Richard J. Saia ,  Jeffrey B. Fortin

IPC: H01L021/302 ,  H01L021/461 ,  H01L021/311

CPC classification number: B81C1/00619 ,  B81B2203/033 ,  B81C1/00412 ,  B81C2201/0132 ,  B81C2201/016 ,  H01L21/0332 ,  H01L21/3065 ,  H01L21/3081 ,  Y10S438/964

Abstract: A method for creating deep features in a Si-containing substrate for use in fabricating MEMS type devices is provided. The method includes first forming a thin Ni hardmask on a surface of a Si-containing substrate. The Ni hardmask is patterned using conventional photolithography and wet etching so as to expose at least one portion of the underlying Si-containing substrate. The at least one exposed portion of the Si-containing substrate, not containing the patterned hardmask, is then etched in a plasma that includes free radicals generated from a gaseous mixture of chlorine (Cl2), sulfur hexafluoride (SF6) and oxygen (O2). The interaction of the gas species in the plasma yields a rapid silicon etch rate that is highly selective to the Ni hardmask. The etch rate ratio of Si to Ni using the inventive method is greater than 250:1.

Abstract translation: 提供了一种用于制造用于制造MEMS型器件的含Si衬底中的深度特征的方法。 该方法包括首先在含Si衬底的表面上形成薄的Ni硬掩模。 使用常规的光刻和湿法刻蚀图案化Ni硬掩模，以暴露下面的含Si衬底的至少一部分。 然后，在包含由氯（Cl 2），六氟化硫（SF 6）和氧（O 2）的气体混合物产生的自由基的等离子体中蚀刻含有图案化的硬掩模的含Si衬底的至少一个暴露部分， 。 等离子体中的气体物质的相互作用产生了对Ni硬掩模高度选择性的快速硅蚀刻速率。 使用本发明方法的Si与Ni的蚀刻速率比大于250:1。

公开(公告)号：US20030176007A1

公开(公告)日：2003-09-18

申请号：US10296771

申请日：2002-12-13

Inventor： Andreas Bertz ,  Thomas Gessner ,  Matthias Kuchler ,  Roman Knofler

IPC: H01L021/00

CPC classification number: B81B3/0086 ,  B81B2203/033 ,  B81C2201/016

Abstract: The invention relates to a microstructure in a preferably electrically conductive substrate (1), more specifically made of doped single crystal silicon, with at least one functional unit (2.1, 2.2) and to a method of fabricating the same. In accordance with the invention, the functional unit (2.1, 2.2) is mechanically and electrically separated from the substrate (1) on all sides by means of isolation gaps (5, 5a) and is connected, on at least one site, to a first structure (4a) of an electrically conductive layer (S) that is electrically isolated from the substrate (1) by way of an isolation layer (3) and that secures the unit into position relative to the substrate (1). For this purpose, the functional unit (2.1, 2.2) is released from the substrate (1) in such a manner that the isolation gaps (5, 5a) are provided on all sides relative to the substrate (1). The electrically conductive layer (S) is applied in such a manner that it is connected through contact fingers (4a) for example to the functional unit (2.1, 2.2) which it secures into position. The method in accordance with the invention permits to substantially facilitate the manufacturing process and to produce a microstructure with but small parasitic capacitances.

Abstract translation: 本发明涉及在具有至少一个功能单元（2.1,2.2）的优选导电衬底（1）中，更具体地由掺杂单晶硅制成的微观结构及其制造方法。 根据本发明，功能单元（2.1,2.2）通过隔离间隙（5,5a）在所有侧面上与基板​​（1）机械地和电气地分开，并且在至少一个位置上连接到 通过隔离层（3）与衬底（1）电绝缘的导电层（S）的第一结构（4a），并且将单元固定在相对于衬底（1）的位置。 为此，功能单元（2.1,2.2）以这样的方式从基板（1）释放，使得隔离间隙（5,5a）相对于基板（1）设置在所有侧面上。 导电层（S）以这样的方式被施加，使得它通过接触指（4a）例如连接到功能单元（2.1,2.2）上，其被固定到位。 根据本发明的方法允许基本上方便制造过程并产生具有小的寄生电容的微结构。