VOLTAGE CONTROLLED OSCILLATOR INCLUDING MUGFETS
    114.
    发明公开
    VOLTAGE CONTROLLED OSCILLATOR INCLUDING MUGFETS 审中-公开
    包含MUFTETS的电压控制振荡器

    公开(公告)号:EP3235122A1

    公开(公告)日:2017-10-25

    申请号:EP15798642.3

    申请日:2015-11-12

    Applicant: Xilinx, Inc.

    Abstract: Voltage-controlled oscillation (100) is described. In an apparatus therefor, an inductor (120) has a tap and has or is coupled to a positive-side output node (105) and a negative side output node (106). The tap is coupled to receive a first current. A coarse grain capacitor array (130) is coupled to the positive-side output node (105) and the negative side output node (106) and is coupled to respectively receive select signals (168). A varactor (140) is coupled to the positive-side output node (105) and the negative side output node (106) and is coupled to receive a control voltage (143). The varactor (140) includes MuGFETs (141, 142). A transconductance cell (150) is coupled to the positive- side output node (105) and the negative side output node (106), and the transconductance cell (150) has a common node (107). A frequency scaled resistor network (160) is coupled to the common node (107) and is coupled to receive the select signals (168) for a resistance for a path for a second current.

    Abstract translation: 描述电压控制振荡(100)。 在其设备中,电感器(120)具有抽头并且具有或者耦合到正侧输出节点(105)和负侧输出节点(106)。 抽头被耦合以接收第一电流。 粗粒度电容器阵列(130)耦合到正侧输出节点(105)和负侧输出节点(106)并且被耦合以分别接收选择信号(168)。 变容二极管(140)耦合到正侧输出节点(105)和负侧输出节点(106)并且被耦合以接收控制电压(143)。 变容二极管(140)包括MuGFET(141,142)。 跨导单元(150)耦合到正侧输出节点(105)和负侧输出节点(106),并且跨导单元(150)具有公共节点(107)。 频率调节电阻网络(160)耦合到公共节点(107)并且被耦合以接收用于第二电流的路径的电阻的选择信号(168)。

    TUNABLE RESONANT CIRCUIT IN AN INTEGRATED CIRCUIT
    115.
    发明公开
    TUNABLE RESONANT CIRCUIT IN AN INTEGRATED CIRCUIT 有权
    可调谐的谐振电路是集成电路

    公开(公告)号:EP2628241A1

    公开(公告)日:2013-08-21

    申请号:EP11754596.2

    申请日:2011-08-31

    Applicant: Xilinx, Inc.

    Abstract: A tunable resonant circuit (102) includes first capacitors (104, 108, 216, 228, 232) and second capacitors (106, 1 10, 218, 230, 234) that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well (320, 326) disposed within a second well (322, 328) in a substrate (324). The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor (120, 130) are respectively coupled to the second electrode (1 14, 304) of the first capacitor and the second electrode (1 18, 308) of the second capacitor. Two channel electrodes of a second transistor (122, 132) are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor (124, 134) are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes (226, 314) of the first, second, and third transistors are responsive to a tuning signal (126, 136), and an inductor (144, 202) is coupled between the first electrodes (1 12, 1 16, 302, 306) of the first and second capacitors.

    Tuning circuit and IGFET
    116.
    发明公开
    Tuning circuit and IGFET 审中-公开
    调整和IGFET

    公开(公告)号:EP1391989A8

    公开(公告)日:2004-07-07

    申请号:EP02255136.0

    申请日:2002-07-23

    Abstract: A tuning circuit comprising a first reactance (12), a second reactance (13) and a insulated gate field effect transistor (11) having a gate arranged to receive a control signal. The first reactance (12) is connected between the source of the field effect transistor (11) and a first node. The second reactance (13) has the same value as the first reactance (12) and is connected between the drain of the field effect transistor (11) and a second node. The first and second nodes are arranged so as to experience a balanced ac signal. Turning the field effect transistor (11) on has the effect of making the first and second reactances (12, 13) effective in the circuit and vice versa. An IGFET has a grounded region (33) surrounding source and drain regions (21, ..., 24, 26, ..., 29). The gate electrode (34) overlies the boundary between the grounded region (33) and the source and drain regions (21, ..., 24, 26, ..., 29).

    Integrierter Hochfrequenzschwingkreis mit Abgleichkondensatoren

    公开(公告)号:EP1146640A1

    公开(公告)日:2001-10-17

    申请号:EP00107704.9

    申请日:2000-04-10

    CPC classification number: H03J3/20 H03B2201/0266 H03J3/185 H03J2200/10

    Abstract: Zu einem Schwingkreis (1) ist ein Leiternetzwerk (12) parallel geschaltet, das Abgleichkondensatoren (18) enthält. Die Abgleichkondensatoren können über PIN-Dioden (17) parallel zu den Kapazitätsdioden (3) im Schwingkreis 1 zugeschaltet werden. Dadurch ist ein Abgleich des Schwingkreises (1) möglich.

    Abstract translation: 该组件具有通过微调二极管设定为预定频率范围的振荡器电容。 振荡电路谐振频率误差由耦合到振荡器电路的导体网络补偿,该导体网络通过具有横向二极管的电容和纵向线之间串联的电容来补偿,用于通过设置具有开关直流电流的横向二极管工作点与振荡器电容并联连接。 网络。 该组件具有振荡器电容,其值可由微调二极管(3)在预定频率范围内设置。 通过耦合电容(11)和串联连接的横向二极管(17)和电容(18),通过耦合到振荡器电路的导体网络(12)来补偿振荡电路(1)的谐振频率的与制造相关的偏差。 在可以通过使用可切换直流设置横向二极管的工作点的可与振荡器电容并联的纵向线之间 网络。

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