Abstract:
A phase detector of a phase-lock-loop circuit measures a phase error between an output signal of an oscillator and a synchronizing signal. When a difference between the phase error that is measured in a pair of horizontal line periods exceeds a first magnitude, that is indicative of phase error inconsistency, the phase of the oscillator output signal is not corrected an the phase-lock-loop circuit operates in an idle mode of operation.
Abstract:
A phase-locked-loop circuit includes an oscillator having switched capacitors that are selectively coupled to a positive feedback path of the oscillator in a coarse frequency error correction mode of operation. When the frequency error is small, the circuit operates in a fine error correction mode without varying the selection of the switched reactive elements.
Abstract:
Voltage-controlled oscillation (100) is described. In an apparatus therefor, an inductor (120) has a tap and has or is coupled to a positive-side output node (105) and a negative side output node (106). The tap is coupled to receive a first current. A coarse grain capacitor array (130) is coupled to the positive-side output node (105) and the negative side output node (106) and is coupled to respectively receive select signals (168). A varactor (140) is coupled to the positive-side output node (105) and the negative side output node (106) and is coupled to receive a control voltage (143). The varactor (140) includes MuGFETs (141, 142). A transconductance cell (150) is coupled to the positive- side output node (105) and the negative side output node (106), and the transconductance cell (150) has a common node (107). A frequency scaled resistor network (160) is coupled to the common node (107) and is coupled to receive the select signals (168) for a resistance for a path for a second current.
Abstract:
A tunable resonant circuit (102) includes first capacitors (104, 108, 216, 228, 232) and second capacitors (106, 1 10, 218, 230, 234) that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well (320, 326) disposed within a second well (322, 328) in a substrate (324). The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor (120, 130) are respectively coupled to the second electrode (1 14, 304) of the first capacitor and the second electrode (1 18, 308) of the second capacitor. Two channel electrodes of a second transistor (122, 132) are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor (124, 134) are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes (226, 314) of the first, second, and third transistors are responsive to a tuning signal (126, 136), and an inductor (144, 202) is coupled between the first electrodes (1 12, 1 16, 302, 306) of the first and second capacitors.
Abstract:
A tuning circuit comprising a first reactance (12), a second reactance (13) and a insulated gate field effect transistor (11) having a gate arranged to receive a control signal. The first reactance (12) is connected between the source of the field effect transistor (11) and a first node. The second reactance (13) has the same value as the first reactance (12) and is connected between the drain of the field effect transistor (11) and a second node. The first and second nodes are arranged so as to experience a balanced ac signal. Turning the field effect transistor (11) on has the effect of making the first and second reactances (12, 13) effective in the circuit and vice versa. An IGFET has a grounded region (33) surrounding source and drain regions (21, ..., 24, 26, ..., 29). The gate electrode (34) overlies the boundary between the grounded region (33) and the source and drain regions (21, ..., 24, 26, ..., 29).
Abstract:
The invention relates to a structural element with an integrated high-frequency circuit. A ladder network (12) is connected in parallel to a resonator circuit (1), said ladder network comprising trimming capacitors (18). Said trimming capacitors can be connected in parallel to the variable capacitance diodes (3) in the resonator circuit (1) via PIN diodes (17), thereby allowing for the resonator circuit (1) to be trimmed.
Abstract:
Zu einem Schwingkreis (1) ist ein Leiternetzwerk (12) parallel geschaltet, das Abgleichkondensatoren (18) enthält. Die Abgleichkondensatoren können über PIN-Dioden (17) parallel zu den Kapazitätsdioden (3) im Schwingkreis 1 zugeschaltet werden. Dadurch ist ein Abgleich des Schwingkreises (1) möglich.