公开(公告)号：WO2021101605A1

公开(公告)日：2021-05-27

申请号：PCT/US2020/046687

申请日：2020-08-17

Applicant: XILINX, INC.

Inventor： SHIN, Jaewook ,  UPADHYAYA, Parag ,  MA, Shaojun

IPC: H03L7/24

Abstract: A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.

公开(公告)号：WO2019231857A1

公开(公告)日：2019-12-05

申请号：PCT/US2019/034026

申请日：2019-05-24

Applicant: XILINX, INC

Inventor： MEGAWER, Karim M. ,  UPADHYAYA, Parag ,  TURKER MELEK, Didem Z. ,  WU, Zhaoyin D.

IPC: H03M3/00 ,  H03M7/36 ,  H03L7/197

Abstract: An example sigma delta modulator (SDM) circuit includes a floor circuit (306), a subtractor (308) having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter (302) having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit (304) having an input coupled to the output of the floor circuit, and an adder (310) having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.

公开(公告)号：WO2017177064A1

公开(公告)日：2017-10-12

申请号：PCT/US2017/026449

申请日：2017-04-06

Applicant: XILINX, INC.

Inventor： NANDWANA, Romesh K. ,  UPADHYAYA, Parag

IPC: H03L7/08 ,  H03L7/099

CPC classification number: H03L7/24 ,  H03L7/0805 ,  H03L7/081 ,  H03L2207/06 ,  H03L2207/50

Abstract: An example clock generator circuit includes a fractional reference generator (202) configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock. The clock generator circuit includes a digitally controlled delay line (DCDL) (308) that delays the reference clock based on a first control code, and a pulse generator (206) configured to generate pulses based on the delayed reference clock. The clock generator circuit includes a digitally controlled oscillator (DCO) (208) configured to generate an output clock based on a second control code, the DCO including an injection input coupled to the pulse generator to receive the pulses. The clock generator circuit includes a phase detector (316) configured to compare the output clock and the reference clock and generate the phase error signal, and a control circuit configured to generate the first and second control codes based on the phase error signal.

Abstract translation: 示例时钟发生器电路包括被配置为响应于基准参考时钟和相位误差信号而生成参考时钟的分数参考发生器（202），所述参考时钟的频率为有理数 基准参考时钟频率的倍数。 时钟发生器电路包括基于第一控制码延迟参考时钟的数字控制延迟线（DCDL）（308），以及配置成基于延迟的参考时钟产生脉冲的脉冲发生器（206）。 时钟发生器电路包括被配置为基于第二控制代码生成输出时钟的数字控制振荡器（DCO）（208），该DCO包括耦合到脉冲发生器以接收脉冲的注入输入。 时钟发生器电路包括被配置为比较输出时钟和参考时钟并且生成相位误差信号的相位检测器（316）以及被配置为基于相位误差信号生成第一和第二控制代码的控制电路。 p>

公开(公告)号：WO2022265704A1

公开(公告)日：2022-12-22

申请号：PCT/US2022/020477

申请日：2022-03-16

Applicant: XILINX, INC.

Inventor： ZHANG, Wenfeng ,  WU, Zhaoyin Daniel ,  UPADHYAYA, Parag

IPC: H04L25/03 ,  H04L25/06 ,  H04L7/00

Abstract: In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.

公开(公告)号：WO2021096613A1

公开(公告)日：2021-05-20

申请号：PCT/US2020/054456

申请日：2020-10-06

Applicant: XILINX, INC.

Inventor： WU, Zhaoyin D. ,  UPADHYAYA, Parag

IPC: H04L25/03 ,  H04L7/00

Abstract: Apparatus and associated methods relate to adapting a continuous time linear equalization circuit with minimum mean square error baud-rate clock and data recovery circuit to be able to lock to the center or near center of an eye diagram. In an illustrative example, a circuit may include an inter-symbol interference (ISI) detector configured to receive data and error samples, a summing circuit coupled to the output of the ISI detector, a moving average filter configured to receive the output of the summing circuit and generate an average output, a voter configured to generate a vote in response to the average output and a predetermined threshold, and, an accumulator and code generator configured to generate a code signal in response to the generated vote. By introducing the moving average filter and the voter, a quicker way to lock to the center or near center of an eye diagram may be obtained.

公开(公告)号：WO2018164834A1

公开(公告)日：2018-09-13

申请号：PCT/US2018/018898

申请日：2018-02-21

Applicant: XILINX, INC.

Inventor： CHO, Junho ,  POON, Chi, Fung ,  UPADHYAYA, Parag

IPC: H03M1/46 ,  H03M1/40

Abstract: An example successive approximation (SAR) analog-to-digital converter (ADC) includes: a track-and-hold (T/H) circuit (202) configured to receive an analog input signal; a digital-to-analog converter (DAC) (203); an adder (204) having inputs coupled to outputs of the T/H circuit and the DAC; a comparison circuit (206) coupled to an output of the adder and configured to perform a comparison operation; and a control circuit (250), coupled to an output of the comparison circuit, configured to: receive a selected resolution; gate the comparison operation of the comparison circuit based on the selected resolution; and generate a digital output signal having the selected resolution.

公开(公告)号：WO2018128733A1

公开(公告)日：2018-07-12

申请号：PCT/US2017/064022

申请日：2017-11-30

Applicant: XILINX, INC.

Inventor： UPADHYAYA, Parag ,  JING, Jing

IPC: H01L23/522

Abstract: An integrated circuit device is described. The integrated circuit device comprises a substrate (202); a plurality of metal routing interconnect layers (710, 712, 716); an inductor (108) formed in at least one metal layer of the plurality of metal routing interconnect layers; and a bottom metal layer (702) between the plurality of metal routing interconnect layers and the substrate; wherein a pattern ground shield (302) is formed in the bottom metal layer. A method of implementing an inductor in an integrated circuit device is also disclosed.

公开(公告)号：WO2017131844A1

公开(公告)日：2017-08-03

申请号：PCT/US2016/062322

申请日：2016-11-16

Applicant: XILINX, INC.

Inventor： HEARNE, Catherine ,  UPADHYAYA, Parag ,  GEARY, Kevin

IPC: H03K5/135 ,  H03K5/00

CPC classification number: H03K5/135 ,  H03K2005/00052 ,  H03K2005/00058

Abstract: A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs (121) coupled to receive a plurality of clock signals; a plurality of transistor pairs (330, 332, 340, 342), each transistor pair having a first transistor coupled to a first output node (310) and a second transistor coupled to a second output node (314), wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load (308) coupled to the first output node; and a second active inductor load (312) coupled to the second output node.

Abstract translation: 描述了在集成电路中实现的用于生成时钟信号的相位内插器。 相位内插器包括多个输入端（121），其被耦合以接收多个时钟信号; 多个晶体管对（330,332,340,342），每个晶体管对具有耦合到第一输出节点（310）的第一晶体管和耦合到第二输出节点（314）的第二晶体管，其中第一时钟信号 与所述晶体管对相关联的所述第一时钟信号耦合到所述第一晶体管的栅极，并且与所述晶体管对相关联的反相的第一时钟信号耦合到所述第二晶体管的栅极; 耦合到第一输出节点的第一有源电感器负载（308） 和耦合到第二输出节点的第二有源电感负载（312）。

公开(公告)号：WO2017078848A1

公开(公告)日：2017-05-11

申请号：PCT/US2016/051100

申请日：2016-09-09

Applicant: XILINX, INC.

Inventor： NAMKOONG, Jinyung ,  ZHANG, Wenfeng ,  UPADHYAYA, Parag

IPC: H03K19/0175

CPC classification number: H03K3/01 ,  H03K19/017527

Abstract: Methods and apparatus are described for a differential active inductor load (500, 510) for inductive peaking in which cross-coupled capacitive elements (M3, M4, M7, M8) are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (C gd ) of transistors (M1, M2, M5, M6) in the active inductor load (500, 510). The cross-coupled capacitive elements (M3, M4, M7, M8) extend the range over which the active inductor load (500, 510) behaves inductively and increase the quality factor (Q) of each active inductor (300, 400). Therefore, the achievable inductive peaking of the load (500, 510) is significantly increased, which leads to providing larger signal swing across the load for a given power or, alternatively, lower power for a given signal swing.

Abstract translation: 描述了用于电感性峰化的差分有源电感器负载（500,510）的方法和装置，其中交叉耦合的电容性元件（M3，M4，M7，M8）被用于抵消，或者 至少减小有源电感器负载（500,510）中的晶体管（M1，M2，M5，M6）的栅极 - 漏极电容（Cgd_）的限制效应。 交叉耦合的电容元件（M3，M4，M7，M8）延伸有源电感负载（500,510）的感应范围，并增加每个有源电感（300,400）的品质因数（Q）。 因此，负载（500,510）的可实现的感应峰化显着增加，这导致给定功率上的负载上的较大信号摆动或者给定信号摆幅下的较低功率。

公开(公告)号：WO2016164075A1

公开(公告)日：2016-10-13

申请号：PCT/US2015/063211

申请日：2015-12-01

Applicant: XILINX, INC.

Inventor： ZHANG, Wenfeng ,  UPADHYAYA, Parag

IPC: H03K19/0185 ,  H03K19/094

CPC classification number: H03K19/018514 ,  H03K19/09432

Abstract: A common mode logic buffer device includes a current source (112) configured to provide a source current. An input stage includes a first MOS transistor pair (110) configured to generate, from the source current and based upon an input differential voltage, a differential current between two output paths. An output stage includes a second MOS transistor pair (106) configured to generate an output differential voltage based upon an effective impedance provided for the each of the two output paths. An adjustment circuit (104, 108) is configured to adjust, in response to a control signal, the effective impedance of the second MOS transistor pair (106).

Abstract translation: 共模逻辑缓冲器件包括被配置为提供源极电流的电流源（112）。 输入级包括被配置为从源电流并基于输入差分电压产生两个输出路径之间的差分电流的第一MOS晶体管对（110）。 输出级包括被配置为基于为两个输出路径中的每一个提供的有效阻抗产生输出差分电压的第二MOS晶体管对（106）。 调整电路（104,108）被配置为响应于控制信号调节第二MOS晶体管对（106）的有效阻抗。