公开(公告)号：US5737547A

公开(公告)日：1998-04-07

申请号：US480739

申请日：1995-06-07

Applicant: William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

Inventor： William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

IPC: G06F9/38 ,  G06F13/36 ,  G06F9/22

CPC classification number: G06F9/3824

Abstract: A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

Abstract translation: 提供非阻塞负载缓冲器用于高速微处理器和存储器系统。 非阻塞负载缓冲器将高速处理器/高速缓存总线接口，该总线将处理器和高速缓存连接到非阻塞负载缓冲区，其中低速外设总线连接到外围设备。 非阻塞负载缓冲器允许以相对较低带宽的外围设备从外围设备的最大速率直接从处理器的编程I / O检索数据，从而可以处理和存储数据，而不会使处理器无需空闲。 可以同时缓冲多处理器内的多个处理器的I / O请求，以便可以在设备的等待时间期间处理多个非阻塞负载。 因此，通过处理器的编程I / O实现来自多个I / O设备的连续最大吞吐量，并且可以减少完成任务和处理数据所需的时间。 此外，提供了多重优先级的非阻塞负载缓冲器，用于通过基于优先级的存储器和外设访问调度来服务运行不同期限的实时处理的多处理器。

公开(公告)号：US5714037A

公开(公告)日：1998-02-03

申请号：US649347

申请日：1996-05-17

Applicant: Kumar D. Puntambekar ,  K. Y. Ramanujam ,  Tom Blount ,  Ray Liang

Inventor： Kumar D. Puntambekar ,  K. Y. Ramanujam ,  Tom Blount ,  Ray Liang

IPC: G03F7/085 ,  H01L21/311 ,  C23F1/00

CPC classification number: G03F7/085 ,  H01L21/31116 ,  Y10S438/974

Abstract: Methods for improving adhesion between various materials utilized in the fabrication of integrated circuits. A first method relates to improving adhesion between a silicon nitride layer and a silicon dioxide layer. The method includes treating a surface of the silicon dioxide layer with a nitrogen plasma in a reactive ion etching process prior to depositing the silicon nitride film on the surface of the silicon dioxide layer. A second method relates to improving adhesion between a silicon nitride layer and a polyimide layer. The method includes the step of treating a surface of the silicon nitride layer with a oxygen/argon plasma in a reactive ion etching process prior to depositing the polyimide layer film on the surface of the silicon nitride layer. A third method relates to improving adhesion between a photoresist layer and a metal. The method includes the step of treating a surface of the photoresist layer with a oxygen/argon plasma in a reactive ion etching process prior to depositing the metal on the surface of the photoresist layer.

Abstract translation: 用于提高在集成电路制造中使用的各种材料之间的粘附性的方法。 第一种方法涉及改善氮化硅层和二氧化硅层之间的粘合性。 该方法包括在将氮化硅膜沉积在二氧化硅层的表面上之前，用反应离子蚀刻工艺中的氮等离子体处理二氧化硅表面。 第二种方法涉及提高氮化硅层和聚酰亚胺层之间的粘合性。 该方法包括在将聚酰亚胺层膜沉积在氮化硅层的表面上之前，在反应离子蚀刻工艺中用氧/氩等离子体处理氮化硅层的表面的步骤。 第三种方法涉及改善光致抗蚀剂层和金属之间的粘合性。 该方法包括在将金属沉积在光致抗蚀剂层的表面上之前，在反应离子蚀刻工艺中用氧/氩等离子体处理光致抗蚀剂层的表面的步骤。

公开(公告)号：US5649160A

公开(公告)日：1997-07-15

申请号：US447565

申请日：1995-05-23

Applicant: Alan G. Corry ,  Graham Y. Mostyn ,  Jean-Yves Michel

Inventor： Alan G. Corry ,  Graham Y. Mostyn ,  Jean-Yves Michel

IPC: H04B15/04 ,  G06F12/00

CPC classification number: H04B15/04 ,  H04B2215/064

Abstract: The present invention encompasses techniques for reducing digital noise in integrated circuits and circuit assemblies, particularly dense mixed-signal integrated circuits, based upon shaping the noise from the digital circuit and concentrating it in a single, or a small number, of parts of the frequency spectrum. Generally, the presence of noise in the analog circuit is less important at certain frequencies, and therefore the spectral peak or peaks from the digital circuit can be carefully placed to result in little or no interference. As an example, a radio receiver might be designed such that the peaks of the digital noise lie between received channels, outside the band edges of each.

Abstract translation: 本发明包括基于整形来自数字电路的噪声并将其集中在频率的单个或少数部分中的集成电路和电路组件，特别是致密混合信号集成电路中的数字噪声的技术 光谱。 通常，在某些频率下，模拟电路中噪声的存在不太重要，因此可以小心地将来自数字电路的频谱峰值或峰值导致很少或没有干扰。 作为示例，可以设计无线电接收机，使得数字噪声的峰值位于接收的信道之间，每个的频带边缘之外。

公开(公告)号：US5535166A

公开(公告)日：1996-07-09

申请号：US280350

申请日：1994-07-25

Applicant: Bruce L. Bateman

Inventor： Bruce L. Bateman

IPC: G11C5/14 ,  G11C7/06 ,  G11C7/02

CPC classification number: G11C5/143 ,  G11C7/062

Abstract: A circuit for isolating an interconnect line from unwanted input signal voltage levels is described. One implementation of the circuit includes a transmission gate coupled in series between an input signal and an interconnect line having its gate coupled to the output of an inverter and the input of the inverter coupled to the input signal. The inverter senses the input signal and when it sense voltages that are either too high or low, the isolation circuit decouples the input signal from the interconnect line such that the input signal can transition independently with respect to the voltage levels on the interconnect line.

Abstract translation: 描述了用于将互连线与不需要的输入信号电压电平隔离的电路。 该电路的一个实施方式包括串联连接在输入信号和互连线之间的传输门，其互连线与其反相器的输出耦合，并且反相器的输入耦合到输入信号。 逆变器检测输入信号，当检测到过高或过低的电压时，隔离电路将输入信号与互连线分离，使得输入信号可以相对于互连线上的电压电平独立地转变。

公开(公告)号：US5500811A

公开(公告)日：1996-03-19

申请号：US377096

申请日：1995-01-23

Applicant: Alan G. Corry

Inventor： Alan G. Corry

IPC: H03H17/02 ,  H03H17/06 ,  G06F15/31 ,  G06F7/38

CPC classification number: H03H17/0275 ,  H03H17/06

Abstract: A compact Finite Impulse Response (FIR) filter using one or both of a compact address sequencer and a compact multiplier/accumulator. The address sequencer exploits certain symmetry properties existing between different phases of a polyphase FIR filter in order to reduce coefficient storage and simplify address sequencing. The multiplier/accumulator is capable of performing two multiply/accumulate operations per clock cycle, avoiding in certain instances the need to add a second multiplier/accumulator. The area required to realize a FIR filter for performing real-time filter is therefore reduced.

Abstract translation: 使用紧凑型地址排序器和紧凑型乘法器/累加器之一或两者的紧凑型有限脉冲响应（FIR）滤波器。 地址序列器利用多相FIR滤波器的不同相之间存在的某些对称性，以减少系数存储并简化地址排序。 乘法器/累加器能够在每个时钟周期执行两次乘法/累加操作，避免在某些情况下需要添加第二个乘法器/累加器。 因此，实现用于执行实时滤波器的FIR滤波器所需的面积减少。

公开(公告)号：US5386140A

公开(公告)日：1995-01-31

申请号：US114980

申请日：1993-08-31

Applicant: James A. Matthews

Inventor： James A. Matthews

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/36 ,  H01L29/732 ,  H01L29/70

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/36 ,  H01L29/732 ,  Y10S148/01

Abstract: A bipolar transistor having an emitter, a base, and a collector includes an intrinsic base region having narrow side areas and a wider central area. The side areas are located adjacent to the extrinsic base region, while the central area is disposed underneath the emitter. The lateral doping profile of the base is tailored so that the doping concentrations in the extrinsic region and the central area are relatively high compared to the doping concentration of the narrow side areas of the intrinsic base. The combination of the narrow side areas and the lateral base doping profile constrains the depletion region within the base thereby lowering punch-through voltage of the transistor without loss of beta.

Abstract translation: 具有发射极，基极和集电极的双极晶体管包括具有窄侧面区域和较宽中心区域的本征基极区域。 侧面区域位于外部基极区域附近，而中央区域设置在发射体下方。 定制基极的横向掺杂分布，使得与本征基极的窄边区域的掺杂浓度相比，外在区域和中心区域中的掺杂浓度相对较高。 窄边区域和横向基极掺杂曲线的组合限制了基极内的耗尽区域，从而降低晶体管的穿通电压而不损失β。

公开(公告)号：US5232047A

公开(公告)日：1993-08-03

申请号：US820365

申请日：1992-01-14

Applicant: James A. Matthews

Inventor： James A. Matthews

IPC: F28F3/12 ,  H01L23/473

CPC classification number: F28F3/12 ,  H01L23/473 ,  F28F2260/02 ,  H01L2924/0002

Abstract: A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates, laminated together to form a block. Each plate has a microscopic recessed portion etched into one face of the plate and a pair of holes cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.

Abstract translation: 适用于冷却诸如半导体集成电路的发热装置的微型层流式热交换器包括多个薄板，层压在一起以形成块体。 每个板具有蚀刻到板的一个面中的微观凹陷部分和穿过板切割的一对孔，使得当形成块时，孔对准以形成一对冷却剂分配歧管。 在层压过程中，歧管通过由凹部形成的多个微细通道相连接。 通过这些通道的冷却液流动可实现除热。

公开(公告)号：US5108945A

公开(公告)日：1992-04-28

申请号：US647709

申请日：1991-01-28

Applicant: James A. Matthews

Inventor： James A. Matthews

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417

CPC classification number: H01L21/28211 ,  H01L21/28525 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/136

Abstract: A process for faricating polysilicon resistors and polysilicon interconnects coupled to MOS field-effect devices in a silicon substrate includes the steps of depositing and etching a first polysilicon layer to form the gates of the MOS devices; then depositing a second layer of polysilicon between the gates. The second polysilicon layer is then etched so that its upper surface is substantially coplanar with the gates. Contact openings are then defined to the source, drain and gate members of the devices through an insulative layer formed over the first and second polysilicon layers. Next, a metal layer is deposited to fill the openings and is patterned to define electrical contacts to the devices. The patterning step also defines the interconnect lines in the metal layer. A third polysilicon layer is then deposited and patterned to define the polysilicon resistors and interconnects.

Abstract translation: 耦合到硅衬底中的MOS场效应器件的多晶硅电阻器和多晶硅互连件的处理过程包括沉积和蚀刻第一多晶硅层以形成MOS器件的栅极的步骤; 然后在所述栅极之间沉积第二层多晶硅。 然后蚀刻第二多晶硅层，使得其上表面与栅极基本上共面。 然后通过形成在第一和第二多晶硅层上的绝缘层将接触开口限定到器件的源极，漏极和栅极部件。 接下来，沉积金属层以填充开口并被图案化以限定到器件的电触点。 图案化步骤还限定了金属层中的互连线。 然后沉积和图案化第三多晶硅层以限定多晶硅电阻器和互连。

公开(公告)号：EP3276486A1

公开(公告)日：2018-01-31

申请号：EP17183101.9

申请日：2017-07-25

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

IPC: G06F7/544

CPC classification number: G06F7/523 ,  G06F7/5045 ,  G06F7/5443 ,  G06F2207/3828

Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations are disclosed.

Abstract translation: 公开了一种用于对需要大量乘法和累加的向量操作数执行外积和外积累积操作的处理器和方法。

公开(公告)号：EP2309382B1

公开(公告)日：2014-12-03

申请号：EP10179602.7

申请日：1999-08-24

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig

IPC: G06F7/483 ,  G06F7/499 ,  G06F9/38 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318 ,  G06F9/30

CPC classification number: G06F9/30014 ,  G06F7/483 ,  G06F7/4991 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3885

Abstract: A general purpose processor with four copies of an access unit, with an access instruction fetch queue A-queue (101-104). Each A-queue (101-104) is coupled to an access register file AR (105-108) which is coupled to two access functional units A (109-116). In a typical embodiment, each thread of the processor may have on the order of sixty-four general purpose registers. The access unit functions independently by four simultaneous threads of execution, and each compute control flow by performing arithmetic and branch instructions and access memory by performing load and store instructions. These access units also provide wide specifiers for wide operand instructions. These eight access functional units A (109-116) produce results for access register files (105-108) and memory addresses to a shared memory system (117-120).