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    Method for preventing tampering of a semiconductor integrated circuit
    121.
    发明公开
    Method for preventing tampering of a semiconductor integrated circuit 有权
    防止与电路篡改方法

    公开(公告)号：EP1429227A3

    公开(公告)日：2006-01-25

    申请号：EP03257713.2

    申请日：2003-12-09

    Applicant: Renesas Technology Corp.

    Inventor： Okuda, Yuichi C/o Renesas Techn. Corp.

    IPC: G06F1/00

    CPC classification number: H01L23/576 ,  G06K19/073 ,  G06K19/07372 ,  G11C11/412 ,  G11C11/4125 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously. Reverse engineering by irradiation with light can be effectively prevented.

    Method for evaluating semiconductor device error and system for supporting the same
    124.
    发明公开
    Method for evaluating semiconductor device error and system for supporting the same 审中-公开
    评估半导体器件错误的方法和用于支持该方法的系统

    公开(公告)号：EP1583007A2

    公开(公告)日：2005-10-05

    申请号：EP05000924.0

    申请日：2005-01-18

    Applicant: Renesas Technology Corp.

    Inventor： Ibe, Hidefumi Hitachi, Ltd. ,  Yahagi, Yasuo Hitachi, Ltd. ,  Kameyama, Hideaki Hitachi, Ltd.

    IPC: G06F17/50 ,  G11C29/00

    CPC classification number: G01R31/31816 ,  G01R31/002 ,  G01R31/2849 ,  G01R31/2881 ,  G01R31/30

    Abstract: When resistivity against errors caused by cosmic ray neutrons in a semiconductor device is evaluated, the storage (120) in the evaluation apparatus stores multiple spectrum data of white neutrons having different spectrum shapes, and multiple SEE counts obtained by the white neutron method using this multiple spectrum data. A computing section (100) performs processing, with respect to each spectrum data, to read out the spectrum data from the storage, divide the data into multiple energy groups, calculates and stores a total flux of each energy group. Furthermore, the computing section reads out from the storage, the SEE counts with respect to each of the multiple spectrum data and the total flux of each energy group, substitutes the SEE counts and the total flux into a simultaneous equation, where a product of matrix elements indicating the total flux of each of the energy groups as to each of the multiple spectrum data and vectors indicating the SEE cross section of each of the energy groups represents the SEE count as to each of the multiple spectrum data, and calculates the SEE cross section for each of the energy groups. Subsequently, the computing section performs a calculation so that parameters are calculated, which determine a formula of the approximate function of the SEE cross section as a function of energy, so that computed values of error counts obtained by integration of multiple spectra and the approximate function sufficiently match the actual measured values thereof. With the processing as described above, there has been achieved an error evaluation in the semiconductor device using white neutrons independent from an accelerator.

    Abstract translation: 当评估半导体器件中由宇宙射线中子引起的误差的电阻率时，评估设备中的存储器（120）存储具有不同光谱形状的白色中子的多个光谱数据，并且使用该倍数通过白色中子法获得多个SEE计数 频谱数据。 计算部（100）针对每个谱数据执行处理以从存储器读出谱数据，将数据划分为多个能量组，计算并存储每个能量组的总通量。 此外，计算部分从存储器中读出关于多个光谱数据中的每一个和每个能量组的总通量的SEE计数，将SEE计数和总通量代入联立方程，其中矩阵 指示关于多个谱数据中的每一个的每个能量组的总通量的元素以及指示每个能量组的SEE截面的向量表示针对多个谱数据中的每一个的SEE计数，并且计算SEE交叉 部分为每个能源组。 随后，计算部分执行计算，从而计算参数，其确定作为能量的函数的SEE截面的近似函数的公式，使得通过多个谱的积分获得的误差计数的计算值和近似函数 充分匹配其实际测量值。 通过如上所述的处理，已经在使用独立于加速器的白色中子的半导体器件中实现了误差评估。

    OFDM demodulation method and semiconductor integrated circuit device
    126.
    发明申请
    OFDM demodulation method and semiconductor integrated circuit device 有权
    OFDM解调方法和半导体集成电路器件

    公开(公告)号：US20040264432A1

    公开(公告)日：2004-12-30

    申请号：US10809898

    申请日：2004-03-26

    Applicant: Renesas Technology Corp.

    Inventor： Toyokazu Hori ,  Hiroshi Nogami ,  Toshihito Habuka ,  Naoto Inokawa ,  Kazuyuki Takada

    IPC: H04J001/00

    CPC classification number: H04L25/061 ,  H04L27/2657 ,  H04L27/2675 ,  H04L27/2679

    Abstract: The invention comprises: processing for receiving an OFDM packet having a preamble and the following data transmission symbol, in which packet the subcarrier interval of the preamble is set wider than that of the data transmission symbol; processing for estimating a DC offset occurring at a receiving side by using the received preamble; processing for correcting the DC offset on the received data transmission symbol, according to the estimation result of the DC offset; and processing for demodulating the DC offset corrected data transmission symbol. Thus, it is possible to estimate a DC offset and then correct the DC offset according to the estimated value, in the OFDM packet with no nul symbol defined there.

    Abstract translation: 本发明包括：接收具有前同步码和后续数据传输符号的OFDM分组的处理，其中前导码的子载波间隔被设置为比数据传输符号的子载波间隔宽; 用于通过使用所接收的前导码来估计在接收侧发生的DC偏移的处理; 根据直流偏移的估计结果对接收到的数据传输符号校正直流偏移的处理; 以及用于解调DC偏移校正数据传输符号的处理。 因此，可以估计DC偏移，然后根据估计值在没有nul符号的OFDM分组中校正DC偏移。

    Nonvolatile memory and method of restoring of failure memory cell
    127.
    发明申请
    Nonvolatile memory and method of restoring of failure memory cell 失效
    非易失性存储器和故障存储器单元的恢复方法

    公开(公告)号：US20040264245A1

    公开(公告)日：2004-12-30

    申请号：US10767627

    申请日：2004-01-30

    Applicant: Renesas Technology Corp.

    Inventor： Ken Matsubara ,  Takayuki Tamura ,  Tomoyuki Fujisawa

    IPC: G11C016/04

    CPC classification number: G11C16/225

    Abstract: An electrically writable/erasable nonvolatile semiconductor memory such as an AND-type or NOR-type flash memory having an array structure, in which numerous memory cells are connected in parallel between common bit lines and source lines, is capable of readily detecting a memory cell in depletion failure which occurs in the event of a power supply cutoff during a memory cell threshold voltage shift-down operation by the writing or erasing operation. In operation, at the entry of a certain command or at the time of power-on, all word lines are unselected and bit line selecting switches are turned on to find the presence of a memory cell having a current flow due to depletion failure with sense amplifiers connected to the bit lines. On finding the presence of a failing cell, a voltage of selection level (VSS or negative voltage) is applied to each word line in turn, with remaining word lines being pulled to an unselection voltage level (negative voltage or VSS).

    Semiconductor device and a method of manufacturing the same
    129.
    发明申请
    Semiconductor device and a method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20040262678A1

    公开(公告)日：2004-12-30

    申请号：US10827295

    申请日：2004-04-20

    Applicant: Renesas Technology Corp.

    Inventor： Yoshito Nakazawa ,  Yuji Yatsuda

    IPC: H01L029/74

    CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    Abstract: Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, pnull type semiconductor region and pnull type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the nnull type single crystal silicon layer 1B is null (nullnullcm), the CHSP is set to satisfy the following equation: CHSPnull3.80null0.148null.

    Abstract translation: 实现沟槽栅型功率MISFET的击穿电压的升高而不增加制造步骤的数量。 在根据本发明的半导体器件的制造方法中，在一个杂质离子注入步骤中同时在栅极线区域中形成p +型半导体区域和p +型场限制环，以使它们进入 与其中形成有栅极引出电极的沟槽接触。 在形成时，假设设置在凹槽外侧的栅极引出电极的宽度为CHSP，并且n +型单晶硅层1B的电阻率为rho（Ω·cm），则将CHSP设定为满足以下 方程式：CHSP <= 3.80 + 0.148rho。

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