公开(公告)号：US20040264245A1

公开(公告)日：2004-12-30

申请号：US10767627

申请日：2004-01-30

Applicant: Renesas Technology Corp.

Inventor： Ken Matsubara ,  Takayuki Tamura ,  Tomoyuki Fujisawa

IPC: G11C016/04

CPC classification number: G11C16/225

Abstract: An electrically writable/erasable nonvolatile semiconductor memory such as an AND-type or NOR-type flash memory having an array structure, in which numerous memory cells are connected in parallel between common bit lines and source lines, is capable of readily detecting a memory cell in depletion failure which occurs in the event of a power supply cutoff during a memory cell threshold voltage shift-down operation by the writing or erasing operation. In operation, at the entry of a certain command or at the time of power-on, all word lines are unselected and bit line selecting switches are turned on to find the presence of a memory cell having a current flow due to depletion failure with sense amplifiers connected to the bit lines. On finding the presence of a failing cell, a voltage of selection level (VSS or negative voltage) is applied to each word line in turn, with remaining word lines being pulled to an unselection voltage level (negative voltage or VSS).

公开(公告)号：US20040174742A1

公开(公告)日：2004-09-09

申请号：US10796995

申请日：2004-03-11

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Motoki Kanamori ,  Takayuki Tamura ,  Kenji Kozakai ,  Atsushi Shikata ,  Shinsuke Asari

IPC: G11C011/34

CPC classification number: G11C16/10 ,  G11C2207/229

Abstract: In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.

公开(公告)号：US20040156242A1

公开(公告)日：2004-08-12

申请号：US10716504

申请日：2003-11-20

Applicant: Renesas Technology Corp.

Inventor： Tetsuya Iida ,  Motoki Kanamori ,  Atsushi Shikata ,  Takayuki Tamura ,  Kunihiro Katayama

IPC: G11C016/04

CPC classification number: G06K19/07732 ,  G06K19/07

Abstract: There is provided a technology to realize high speed data transfer while compatibility of a card type storage device comprising a nonvolatile memory is ensured. Namely, in the card type storage device comprising the nonvolatile memory, a plurality of data terminals are provided and an interface unit is provided with a circuit for determining levels of data terminals. Some or all of the plurality of data terminals are connected with pull-up resistors for pulling up to a power source voltage. When the determination circuit determines that the data terminals connected with the pull-up resistors are in an open condition, the determination circuit switches a bus width (number of bits) of data.

Abstract translation: 提供了一种实现高速数据传输的技术，同时确保包括非易失性存储器的卡式存储装置的兼容性。 也就是说，在包括非易失性存储器的卡型存储装置中，提供多个数据终端，并且接口单元设置有用于确定数据终端电平的电路。 多个数据端子中的一些或全部与上拉电阻相连以提升电源电压。 当确定电路确定与上拉电阻器连接的数据端子处于打开状态时，确定电路切换数据的总线宽度（位数）。

公开(公告)号：US20040065744A1

公开(公告)日：2004-04-08

申请号：US10667663

申请日：2003-09-23

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Atsushi Shiraishi ,  Takayuki Tamura ,  Chiaki Kumahara ,  Shinsuke Asari

IPC: G06K019/06

CPC classification number: G11C16/3418 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7205 ,  G06F2212/7207 ,  G11C16/349

Abstract: The present invention provides a memory card in which stored information is not lost undesirably even when an operation power source is shut down during an erasing/writing process. A nonvolatile memory has an erase table in which a free-space information flag is associated with each physical address of a memory area and an address translation table in which a physical address of a memory area is associated with each logical address. The free-space information flag indicates whether a corresponding memory area is permitted to be erased or not. A control circuit determines a memory area to which rewrite data is to be written by referring to the free-space information flag of the erase table, reflects the physical address and the logical address of the memory area to which the data is written into the address translation table, and updates the free-space information flag of the erase table. The memory area to which rewrite data is to be written is determined by referring to the free-space information flag of the erase table, and rewriting is not performed in the same memory area.

Abstract translation: 本发明提供一种存储卡，其中即使在擦除/写入处理期间操作电源被关闭时，存储信息也不会不期望地丢失。 非易失性存储器具有擦除表，其中空闲信息标志与存储区域的每个物理地址相关联，以及地址转换表，其中存储区域的物理地址与每个逻辑地址相关联。 自由空间信息标志指示是否允许擦除对应的存储区域。 控制电路通过参照擦除表的自由空间信息标志来确定要写入重写数据的存储器区域，将数据写入地址的存储区域的物理地址和逻辑地址反映 翻译表，并更新擦除表的空闲信息标志。 通过参照擦除表的自由空间信息标志确定要写入重写数据的存储区域，并且不在同一存储区域中进行重写。

公开(公告)号：US20040193928A1

公开(公告)日：2004-09-30

申请号：US10712996

申请日：2003-11-17

Applicant: Renesas Technology Corp.

Inventor： Shinichi Shuto ,  Takayuki Tamura ,  Chiaki Kumahara

IPC: G06F001/26

CPC classification number: G06F1/305

Abstract: Disclosed herewith is a semiconductor processing system such as a card type electronic device, which can easily cope with an error caused by power shutoff that occurs when the card is ejected. The semiconductor processing system is provided with an interface control circuit and a processing circuit and receives operation power from an external device such as a card slot when it is inserted therein. According to a first aspect of the present invention for coping with an error caused by power shutoff that occurs when the card is ejected, the interface control circuit, when the card is ejected from the card slot, detects a potential change to occur at a first external terminal to be disconnected from a predetermined terminal of the card slot before the power supply from the card slot is shut off, then instructs the processing circuit that is active to perform an ending processing. The semiconductor processing system can end the processing by itself before the power supply stops completely.

Abstract translation: 这里公开了一种诸如卡型电子设备的半导体处理系统，其可以容易地处理当卡被弹出时发生的由电源关闭引起的错误。 半导体处理系统设置有接口控制电路和处理电路，并且当插入其中时从诸如卡槽的外部设备接收操作电力。 根据本发明的第一方面，为了应对当卡被弹出时发生的由电源关闭引起的错误，当卡从卡插槽中弹出时，接口控制电路检测到第一次发生的潜在变化 在从卡槽供电之前将外部终端从卡槽的预定终端断开，然后指示有效的处理电路执行结束处理。 在电源完全停止之前，半导体处理系统可以自行结束处理。

公开(公告)号：US20040177216A1

公开(公告)日：2004-09-09

申请号：US10721362

申请日：2003-11-26

Applicant: Renesas Technology Corp.

Inventor： Shinsuke Asari ,  Takayuki Tamura ,  Atsushi Shiraishi

IPC: G06F012/08

CPC classification number: G06F12/0246 ,  G11C16/102

Abstract: A nonvolatile memory has plural memory blocks, each having a plurality of sub memory blocks, and is capable of programming to a first sub memory block within a first memory block and a second sub memory block within a second memory block in parallel. The first sub memory block has a management area for storing a management information including linking information between the first sub memory block corresponding sub memory blocks of other memory blocks. A control circuit controls reading the linking information from the first sub memory block in accordance with address information, and programming to the first sub memory block in accordance with the address information and corresponding sub memory blocks by the linking information.

Abstract translation: 非易失性存储器具有多个存储块，每个存储块具有多个子存储块，并且能够并行地编程到第一存储块内的第一子存储块和第二存储块内的第二子存储块。 第一子存储块具有用于存储管理信息的管理区域，该管理信息包括第一子存储块对应的其他存储块的子存储块之间的链接信息。 控制电路根据地址信息控制从第一子存储块读取链接信息，并根据地址信息和对应的子存储块通过链接信息对第一子存储块进行编程。