公开(公告)号：US20140315534A1

公开(公告)日：2014-10-23

申请号：US14343080

申请日：2012-10-04

Applicant: ST-Ericsson SA

Inventor： Marc Soler ,  Eric Alliot

IPC: H04L27/26 ,  H04W8/08

CPC classification number: H04L27/2601 ,  H04L25/0224 ,  H04L25/025 ,  H04L27/0008 ,  H04L27/2089 ,  H04W8/08

Abstract: Method of data processing for selectively activating, at a mobile station (1, 2), a mode of communication related to VAMOS-2 technology, the method comprising the steps of:—receiving a first signal of a first subchannel (C1), the first signal containing a first training sequence (mwant), and receiving a second signal of a second subchannel (C2), the second signal containing a second training sequence (mosc), the second signal being orthogonally multiplexed with respect to the first signal,—using the first training sequence and the second training sequence to:—determine a value of a parameter (α) defining a ratio between the first subchannel power and the second subchannel power, and—determine a signal to noise ratio estimation, and—determining, using the parameter value and the signal to noise estimation, whether the said mode of communication has to be activated.

Abstract translation: 一种数据处理方法，用于在移动站（1,2）处选择性地激活与VAMOS-2技术相关的通信模式，所述方法包括以下步骤： - 接收第一子信道（C1）的第一信号， 第一信号包含第一训练序列（mwant），以及接收第二子信道（C2）的第二信号，所述第二信号包含第二训练序列（mosc），所述第二信号相对于所述第一信号正交多路复用， 使用所述第一训练序列和所述第二训练序列来：确定定义所述第一子信道功率和所述第二子信道功率之间的比率的参数（α）的值，并且确定信噪比估计， 使用参数值和信噪比估计，是否必须激活所述通信模式。

公开(公告)号：US20140300421A1

公开(公告)日：2014-10-09

申请号：US14113295

申请日：2012-05-01

Applicant: ST-Ericsson SA

Inventor： Vincent Knopik

IPC: H03F3/193 ,  H03F3/24

CPC classification number: H03F3/193 ,  H01L27/0251 ,  H03F1/0261 ,  H03F1/223 ,  H03F1/3205 ,  H03F1/52 ,  H03F1/523 ,  H03F3/19 ,  H03F3/245 ,  H03F2200/18 ,  H03F2200/27 ,  H03F2200/451 ,  H03F2200/471

Abstract: A Power amplifier circuit based on a cascode structure and to be powered by a power source voltage, e.g. a battery, said circuit comprising—a first transistor having a grid, source and drain terminal; said first transistor being connected in a common source mode;—a second grid source transistor having grid, source and drain terminal, said second transistor being connected in common grid mode;—a biasing circuit for biasing said first transistor and said second transistor. The PA is characterized in that it includes a circuit for sensing the value of the power source voltage and for generating at least a first and a second biasing voltage for the grid of said second transistor in accordance with the power source voltage sensed, said first biasing voltage providing substantially equal protection to said first and second transistors when said power source voltage is sensed to be at a high voltage and said second biasing voltage providing more voltage to said first transistor when said power source voltage is sensed to be at a low voltage.

Abstract translation: 基于共源共栅结构并由电源电压供电的功率放大器电路，例如， 电池，所述电路包括：具有栅极，源极和漏极端子的第一晶体管; 所述第一晶体管以公共源模式连接; - 具有栅极，源极和漏极端子的第二栅极源晶体管，所述第二晶体管以公共栅格模式连接; - 偏置电路，用于偏置所述第一晶体管和所述第二晶体管。 PA的特征在于，其包括用于感测电源电压的值的电路，并且用于根据感测的电源电压产生用于所述第二晶体管的电网的至少第一和第二偏置电压，所述第一偏置 当所述电源电压被感测为高电压时，所述电压提供与所述第一和第二晶体管基本相同的保护，并且当所述电源电压被感测为低电压时，所述第二偏置电压向所述第一晶体管提供更多的电压。

公开(公告)号：US20140266829A1

公开(公告)日：2014-09-18

申请号：US14351111

申请日：2012-10-10

Applicant: ST-Ericsson SA

Inventor： Carlo Pinna

IPC: H03M3/00

CPC classification number: H03M3/30 ,  H03M3/39 ,  H03M3/424 ,  H03M3/454

Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator, a digital integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The feedback analog signal is injected via the feedback path and the computation block directly at the input terminal of the quantizer. The converter allows reduction of the complexity of the quantizer.

Abstract translation: 多电平Σ-Δ模数转换器使用具有降低量化级别的量化器来提供多电平输出。 转换器包括直接路径，其包括计算块，模拟积分器，数字积分器和具有降低的量化级别的量化器。 此外，转换器包括反馈路径，其被布置为向计算块提供反馈模拟信号。 反馈模拟信号通过反馈路径和计算块直接在量化器的输入端注入。 该转换器允许降低量化器的复杂性。

公开(公告)号：US20140247028A1

公开(公告)日：2014-09-04

申请号：US14350253

申请日：2012-09-27

Applicant: ST-Ericsson SA

Inventor： Alexandre Pons ,  Frédéric Lebon

IPC: G05F1/575

CPC classification number: G05F1/575 ,  G05F1/10

Abstract: The present invention concerns a low dropout (LDO) regulator of regulating an output signal, the LDO regulator comprising an input stage (15) and an output stage (17), the input stage being adapted to receive a reference signal (VREF) and a feed-back signal (VF) depending on an output signal (VOUT), and to output an intermediate signal based on the feedback signal and on the reference signal, wherein the LDO regulator further comprises a gain stage (16) having a given gain value, which is configurable and wherein the output signal is regulated based on the gain value of the gain stage and on the intermediate signal.

Abstract translation: 本发明涉及调节输出信号的低压差（LDO）调节器，LDO调节器包括输入级（15）和输出级（17），输入级适于接收参考信号（VREF）和 根据输出信号（VOUT）反馈信号（VF），并且基于反馈信号和参考信号输出中间信号，其中LDO调节器还包括具有给定增益值的增益级（16） ，其是可配置的，并且其中基于增益级的增益值和中间信号来调节输出信号。

公开(公告)号：US20140232364A1

公开(公告)日：2014-08-21

申请号：US13963087

申请日：2013-08-09

Applicant: ST-Ericsson SA

Inventor： Matthieu Thomas ,  Patrik Arno ,  Vladimir Molata ,  Ondrej Tlaskal

IPC: H02M3/158

CPC classification number: H02M3/1588 ,  H02M7/483 ,  H02M2001/0003 ,  H02M2001/0009 ,  Y02B70/1466

Abstract: A power conversion circuit uses smaller, cheaper, and faster analog and digital circuits, e.g., buffers, comparators, and processing circuits, to provide the information necessary to control a multilevel power converter faster, cheaper, and with a smaller footprint than conventional techniques. For example, a current detection circuit indirectly measures a direction of a current through an inductor connected between midpoint node and an output node of a multilevel power converter based on comparisons between voltages associated with the multilevel power converter. A capacitor voltage detection detects a capacitor voltage across the flying capacitor to generate a logic signal based on a comparison between the capacitor voltage and a first reference voltage. A control circuit selects an operating state of the multilevel power converter to regulate a first capacitor voltage across the first capacitor based on the indirectly measured direction of the inductor current, the logic signal, and an input command signal.

Abstract translation: 功率转换电路使用更小，更便宜和更快的模拟和数字电路，例如缓冲器，比较器和处理电路，以提供与传统技术相比更快，更便宜和更小占地面积来控制多电平功率转换器所需的信息。 例如，电流检测电路基于与多电平功率转换器相关联的电压的比较，间接地测量通过连接在多电平电力转换器的中点节点和输出节点之间的电感器的电流的方向。 电容器电压检测检测跨越飞行电容器的电容器电压，以基于电容器电压和第一参考电压之间的比较来产生逻辑信号。 控制电路基于间接测量的电感器电流方向，逻辑信号和输入命令信号，选择多电平电力转换器的工作状态来调节跨第一电容器的第一电容器电压。

公开(公告)号：US20140218117A1

公开(公告)日：2014-08-07

申请号：US14240477

申请日：2012-08-14

Applicant: ST-ERICSSON SA

Inventor： Xavier Branca ,  David Chesneau

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M3/156

Abstract: The present invention relates to a voltage regulating device comprising a power stage (30) comprising an inductor (L) between a first node (P1) and a second node (P2); a first switch (A) between the first node (Pi) and a power supply node (P3) for which the potential (Vbat) is non-zero and of constant polarity; a first capacitor (CNEG) between a node (P5) at a reference potential and a second switch (B) coupled to the first node (P1); a second capacitor (CPOS) between a node (P7) at the reference potential and a third switch (C) coupled to the second node (P2); a fourth switch (D) between the second node (P2) and a node (P8) at the reference potential; a fifth switch (E) between the first node (P1 and a node (P9) at the reference potential; a first output (P4) for delivering a first voltage corresponding to the voltage at the terminals of the first capacitor (CNEG); a second output (P6) for delivering a second voltage corresponding to the voltage at the terminals of the second capacitor (CPOS); The power stage further comprises at least one comparator (40, 41) arranged to detect an inversion of the current in the inductor and the power stage is further arranged to close the fourth and fifth switches and to open the first, second and third switches upon detection of an inversion of the current in the inductor.

Abstract translation: 电压调节装置技术领域本发明涉及一种电压调节装置，包括在第一节点（P1）和第二节点（P2）之间包括电感器（L）的功率级（30） 第一节点（Pi）和电位（Vbat）为非零且恒定极性的电源节点（P3）之间的第一开关（A） 在参考电位的节点（P5）与耦合到第一节点（P1）的第二开关（B）之间的第一电容器（CNEG）; 在参考电位的节点（P7）和耦合到第二节点（P2）的第三开关（C）之间的第二电容器（CPOS）; 在第二节点（P2）和参考电位的节点（P8）之间的第四开关（D） 在第一节点（P1和参考电位处的节点（P9）之间的第五开关（E）;用于传送对应于第一电容器（CNEG）的端子处的电压的第一电压的第一输出（P4）; 第二输出（P6），用于传送对应于在第二电容器（CPOS）的端子处的电压的第二电压;功率级还包括至少一个比较器（40,41），其被布置成检测电感器中的电流的反相 并且功率级还被布置成闭合第四和第五开关，并且在检测到电感器中的电流的反转时打开第一，第二和第三开关。

公开(公告)号：US08766683B2

公开(公告)日：2014-07-01

申请号：US13946411

申请日：2013-07-19

Applicant: ST-Ericsson SA

Inventor： Marc Houdebine ,  Julien Kieffer ,  Sebastien Rieubon

IPC: H03L7/18 ,  H03L7/093

CPC classification number: H03L7/0891 ,  H03L7/0895 ,  H03L7/093

Abstract: According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of α*I and the second current has a magnitude of β*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (α−β)*I.

Abstract translation: 根据实施例，描述了具有例如单个电荷泵的双路径环路滤波器电路。 在DPLF电路中的电流流动被设计成在注入时间段期间将源自环路滤波器的第一电流源自环路滤波器，也可以在注入时间段期间从环路滤波器引出第二电流，其中第一电流具有幅度 并且所述第二电流具有大于所述环路滤波器的第三电流，并且在线性化时间段期间从所述环路滤波器吸收第三电流，其中所述第三电流的幅度为（α＆bgr）* I 。

公开(公告)号：US20140153456A1

公开(公告)日：2014-06-05

申请号：US13692782

申请日：2012-12-03

Applicant: ST-ERICSSON SA

Inventor： CHESTER SUNGCHUNG PARK ,  BJORN ANDERS GUSTAVSSON

IPC: H04W52/38

CPC classification number: H04W52/38 ,  H04W52/223 ,  H04W52/288 ,  H04W52/325

Abstract: A UE communication device is provided having a transmitter architecture that transmits SRS transmissions and PUSCH transmissions. A reference mode chosen from a LPM, an MPM and an HPM is selected based on a present power mode of the SRS transmission or based on a predicted power mode that the PUSCH transmission following the present SRS transmission will likely operate in. The transmitter architecture has an exemplary extended switching point structure allowing the RPD between the SRS transmission used for pre-quarter selection and the subsequent PUSCH transmission applying the pre-quarter to be minimized.

Abstract translation: 提供具有发送SRS传输和PUSCH传输的发射机架构的UE通信设备。 从LPM，MPM和HPM选择的参考模式基于SRS传输的当前功率模式或者基于当前SRS传输之后的PUSCH传输将可能操作的预测功率模式来选择。发射机架构具有 允许用于前四分之一选择的SRS传输之间的RPD和应用前四分之一的后续PUSCH传输的示范性扩展切换点结构被最小化。

公开(公告)号：US20140128091A1

公开(公告)日：2014-05-08

申请号：US14116523

申请日：2012-04-24

Applicant: ST-Ericsson SA

Inventor： Bjorn Engström

IPC: H04W48/18 ,  H04W88/06

CPC classification number: H04W48/18 ,  H04W88/06

Abstract: An apparatus (200) for use in a telecommunications system. The apparatus (200) comprising a memory (240) and a controller (210). The controller (210) is configured to receive a radio frequency bandwidth and identify a first candidate carrier frequency (710) from the received a radio frequency bandwidth. The controller is further configured to, for a first potential radio access technology determine a probability estimate (Prob) for the first candidate carrier frequency (710) being a carrier frequency of the first potential radio access technology, where in the probability estimate is based on a received power in a transmission band of the first potential radio access technology having the candidate carrier frequency (710) and on a received power in a guard band of the first potential radio access technology having the candidate carrier frequency and from this select a radio access technology based on the probability estimate (Prob) for the candidate carrier frequency (710).

Abstract translation: 一种用于电信系统的装置（200）。 装置（200）包括存储器（240）和控制器（210）。 控制器（210）被配置为从接收的射频带宽接收射频带宽并识别第一候选载波频率（710）。 控制器进一步被配置为，对于第一潜在无线电接入技术，确定作为第一潜在无线电接入技术的载波频率的第一候选载波频率（710）的概率估计（Prob），其中概率估计基于 具有候选载波频率（710）的第一潜在无线电接入技术的传输频带中的接收功率和具有候选载波频率的第一潜在无线电接入技术的保护频带中的接收功率，并且从其选择无线接入 基于候选载波频率的概率估计（Prob）的技术（710）。

公开(公告)号：US20140120849A1

公开(公告)日：2014-05-01

申请号：US13664014

申请日：2012-10-30

Applicant: ST-ERICSSON SA

Inventor： JANNE OLAVI PELTONEN

IPC: H04B1/40

CPC classification number: H04B17/10 ,  H03H7/40 ,  H04B1/40 ,  H04B17/103 ,  H04B17/12 ,  H04B17/13

Abstract: The invention provides circuitry integrated into a silicon chip that measures aspects of an RF signal on a transmission line in order to provide data that is ultimately used by an antenna tuner circuit to substantially match the impedance of the antenna with that of the transmission line providing the RF frequency to be transmitted.

Abstract translation: 本发明提供集成到硅芯片中的电路，其测量传输线上的RF信号的各方面，以便提供最终由天线调谐器电路使用的数据，以将天线的阻抗与传输线的阻抗基本匹配， RF频率要传输。