公开(公告)号：US11281514B2

公开(公告)日：2022-03-22

申请号：US16693103

申请日：2019-11-22

Applicant: STMicroelectronics Application GmbH

Inventor： Roberto Colombo

IPC: G06F13/42 ,  G06F11/07 ,  G06F1/10 ,  G06F1/12

Abstract: A processing system includes a timer circuit and a processing circuit. The timer circuit is configured to generate a system time signal. The processing circuit is configured to receive the system time signal, detect whether the system time signal reaches or exceeds a given reference value, and start execution of a given processing operation in response to the detection. The timer circuit has associated an error code calculation circuit configured to compute a first set of error detection bits as a function of bits of the system time signal. The processing circuit has an associated error detection circuit configured to: compute a second set of error detection bits as a function of the bits of the system time signal received, compare the first set of error detection bits with the second set of error detection bits, and generate an error signal in response to the comparison.

公开(公告)号：US11093658B2

公开(公告)日：2021-08-17

申请号：US15975460

申请日：2018-05-09

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Grossier ,  Giovanni Disirio

IPC: G06F21/83 ,  G06F21/64 ,  G06F12/02 ,  G06F9/38 ,  G06F9/445 ,  H04L9/32 ,  G06F21/57 ,  G09C1/00 ,  G06F21/74 ,  H04W12/106 ,  H04L29/06 ,  H04W4/40 ,  H04W12/03 ,  H04W12/40

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.

公开(公告)号：US11057194B2

公开(公告)日：2021-07-06

申请号：US16022033

申请日：2018-06-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

Inventor： Roberto Colombo ,  Guido Marco Bertoni ,  William Orlando ,  Roberta Vittimani

IPC: H04L9/08 ,  G06F13/36 ,  H04L9/14 ,  H04L9/32

Abstract: A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.

公开(公告)号：US20200319876A1

公开(公告)日：2020-10-08

申请号：US16829280

申请日：2020-03-25

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F8/654 ,  G06F12/10 ,  G06F11/27

Abstract: A processing system includes a digital processing unit, one or more non-volatile memories configured to store a firmware to be executed by the digital processing unit, a diagnostic circuit configured to execute a self-test operation of the processing system in response to a diagnostic mode enable signal, and a reset circuit. The reset circuit is configured to perform a complex reset of the processing system by generating a first reset of the processing system in response to a given event and generating a second reset of the processing system once the self-test operation has been executed. The processing system is configured to set the diagnostic mode enable signal in response to the first reset, thereby activating execution of the self-test operation.

公开(公告)号：US20200272589A1

公开(公告)日：2020-08-27

申请号：US16874055

申请日：2020-05-14

Applicant: STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US10740267B1

公开(公告)日：2020-08-11

申请号：US16503243

申请日：2019-07-03

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

Inventor： Nirav Prashantkumar Trivedi ,  Sandip Atal ,  Rolf Nandlinger

IPC: G06F13/00 ,  G06F13/28 ,  H03M1/38 ,  H03M1/12

Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.

公开(公告)号：US20190272211A1

公开(公告)日：2019-09-05

申请号：US16289425

申请日：2019-02-28

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F11/07

Abstract: A processing system includes a processing unit configured to be connected to a memory with error detection and/or correction. The processing unit generates at least one read request for reading data from the memory, the read request including an address signal identifying an address of a given memory area in the memory. The processing system includes an error handling circuit connected to the memory for receiving an error signal containing an error code indicating whether the data read from the memory contains errors. The error handling circuit includes a hardware circuit configured to set a first error signal to the error code of the error signal when the address indicated by the address signal belongs to a first address range and to set a second error signal to the error code of the error signal when the address indicated by the address signal belongs to a second address range.

公开(公告)号：US10375774B2

公开(公告)日：2019-08-06

申请号：US15216561

申请日：2016-07-21

Applicant: STMicroelectronics S.r.l ,  STMicroelectronics Application GMBH

Inventor： Manuel Gaertner ,  Sergio Lecce ,  Giovanni Luca Torrisi

IPC: H05B33/08 ,  B60Q1/14

Abstract: An integrated device for driving a lighting load, such as a LED, has a first memory element, configured to store a nominal duty-cycle at a nominal supply voltage. An actual voltage acquisition element is configured to detect an actual supply voltage. A processing unit is coupled to the first memory element and to the actual voltage acquisition element and configured to calculate a voltage compensated duty-cycle. A driver unit is coupled to the processing unit and is configured to be supplied according to the voltage compensated duty-cycle.

公开(公告)号：US20180330123A1

公开(公告)日：2018-11-15

申请号：US15965802

申请日：2018-04-27

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Roberto COLOMBO ,  Nicolas BERNARD GROSSIER ,  Giovanni DISIRIO ,  Lorenzo RE FIORENTIN

IPC: G06F21/71 ,  H04L9/06 ,  G06F11/07

CPC classification number: G06F21/71 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0772 ,  G06F21/57 ,  G06F21/602 ,  G06F21/77 ,  H03K19/17728 ,  H04L9/0618 ,  H04L2209/12 ,  H04L2209/127

Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.

公开(公告)号：US20180329774A1

公开(公告)日：2018-11-15

申请号：US15975507

申请日：2018-05-09

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics Application GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Grossier ,  Roberta Vittimani

IPC: G06F11/08 ,  G06F11/30 ,  G06F11/00

Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.