公开(公告)号：WO2005104186A2

公开(公告)日：2005-11-03

申请号：PCT/US2005002460

申请日：2005-01-26

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  KOSTENKO JOHN WILLIAMS ,  O'MEARA DAVID L

Inventor： KOSTENKO JOHN WILLIAMS ,  O'MEARA DAVID L

IPC: B08B7/00 ,  C23C16/44 ,  C23C16/458 ,  C23C16/509 ,  H01J37/32 ,  H01L21/00

CPC classification number: H01J37/32862 ,  B08B7/0035 ,  C23C16/4405 ,  C23C16/4581 ,  C23C16/4584 ,  C23C16/509 ,  H01J37/32935 ,  H01J37/32972 ,  H01J37/3299

Abstract: A method for plasma-enhanced cleaning of a system component (21, 25, 26, 35, 94, 104, 112, 116, 126) in a batch-type processing system and a method for monitoring and controlling the cleaning. The cleaning is performed by introducing a cleaning gas in a process chamber (10, 102) of the batch-type processing system (1, 100), forming a plasma by applying power to a system component (21, 25, 26, 35, 94, 104, 112, 116, 126) within the process chamber (10, 102), exposing a material deposit in the process chamber (10, 102) to the plasma to form a volatile reaction product, and exhausting the reaction product from the processing system (1, 100). Monitoring of the processing system (1, 100) can be carried out to determine cleaning status of the processing system (1, 100) and based upon the status from the monitoring, the processing system (1, 100) is controlled for either continuing the exposing and monitoring or stopping the cleaning process. A batch-type processing system (1, 100) is provided that allows plasma-enhanced cleaning of system components (21, 25, 26, 35, 94, 104, 112, 116, 126), and a system (1, 100) is provided with monitoring and controlling capability.

Abstract translation: 用于间歇式处理系统中的系统部件（21,25,26,35,94,104,112,116,126）的等离子体增强清洁的方法以及用于监视和控制清洁的方法。 通过在分批式处理系统（1,100）的处理室（10,102）中引入清​​洁气体来进行清洁，通过向系统组件（21,25,26,35， 在所述处理室（10,102）内，将所述处理室（10,102）中的材料沉积物暴露于所述等离子体以形成挥发性反应产物，并从所述处理室（10,102）中排出所述反应产物 处理系统（1,100）。 可以执行处理系统（1,100）的监视以确定处理系统（1,100）的清洁状态，并且基于来自监视的状态，处理系统（1,100）被控制为继续 曝光和监视或停止清洁过程。 提供了一种分批式处理系统（1,100），其允许对系统组件（21,25,26,35,94,104,112,116,126）进行等离子体增强清洁，以及系统（1,100） 提供监控和控制能力。

公开(公告)号：WO2005096358A1

公开(公告)日：2005-10-13

申请号：PCT/US2005/000661

申请日：2005-01-10

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  DIP, Anthony ,  ROY, Pradip, K. ,  KAUSHAL, Sanjeev ,  LEITH, Allen, J. ,  OH, Seungho ,  JOE, Raymond

Inventor： DIP, Anthony ,  ROY, Pradip, K. ,  KAUSHAL, Sanjeev ,  LEITH, Allen, J. ,  OH, Seungho ,  JOE, Raymond

IPC: H01L21/28

CPC classification number: H01L21/31604 ,  H01L21/02142 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/02362 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/3185 ,  Y10T29/41

Abstract: A method for using a silicon germanium (SiGe) surface layer (160) to integrate a high-k dielectric layer (180) into a semiconductor device. The method forms a SiGe surface layer (160) on a substrate (150) and deposits a high-k dielectric layer (180) on the SiGe surface layer (160). An oxide layer (170), located between the high-k dielectric layer (180) and an unreacted portion of the SiGe surface layer (160), is formed during one or both of deposition of the high-k dielectric layer (180) and an annealing process after deposition of the high-k dielectric layer (180). The method further includes forming an electrode layer (190) on the high-k dielectric layer (180).

Abstract translation: 一种使用硅锗（SiGe）表面层（160）将高k电介质层（180）集成到半导体器件中的方法。 该方法在衬底（150）上形成SiGe表面层（160），并在SiGe表面层（160）上沉积高k电介质层（180）。 在高k电介质层（180）的沉积的一个或两个中，形成位于高k电介质层（180）和SiGe表面层（160）的未反应部分之间的氧化物层（170） 沉积高k电介质层（180）后的退火工艺。 该方法还包括在高k电介质层（180）上形成电极层（190）。

公开(公告)号：WO2005096352A2

公开(公告)日：2005-10-13

申请号：PCT/US2005/000916

申请日：2005-01-12

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  ROY, Pradip, K. ,  DIP, Anthony ,  LEITH, Allen, J. ,  OH, Seungho

Inventor： ROY, Pradip, K. ,  DIP, Anthony ,  LEITH, Allen, J. ,  OH, Seungho

IPC: H01L21/00

CPC classification number: H01L21/67109 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2807 ,  H01L29/161

Abstract: A SiGe thin layer semiconductor structure containing a substrate (400, 500, 600) having a dielectric layer (410, 510, 610), a variable composition Si x Ge 1 - x layer (440, 520, 620) on dielectric layer (410, 510, 610), and a Si cap layer (450, 530, 630) on the variable composition Si x Ge 1x layer (440, 520, 620). The variable composition Si x Ge 1 - x layer (440, 520, 620) can contain a Si x Ge 1-x layer (520, 620) with a graded Ge content or a plurality of Si x Ge 1-x . sub-layers (420, 430) each with different Ge content (421, 431). In one embodiment of the invention, the SiGe thin layer semiconductor structure contains a semiconductor substrate (600) having a dielectric layer (610), a Si­-containing seed layer (615) on the dielectric layer (610), a variable composition Si x Ge 1 - x layer (620) on the seed layer (615), and a Si cap layer (630) on the variable composition Si x Ge 1-x layer (620). A method and processing tool (1, 100) for fabricating the SiGe thin layer semiconductor structure are also provided.

Abstract translation: 一种SiGe薄层半导体结构，其包含在电介质层（410,510,620）上具有介电层（410,510,610），可变组成物SixGe1-x层（440,520,620）的衬底（400,500,600） 610）和可变组成SixGe1x层（440,520,620）上的Si覆盖层（450,530,630）。 可变成分SixGe1-x层（440,520,620）可以包含具有分级Ge含量或多个SixGe1-x的SixGe1-x层（520,620）。 每个具有不同Ge含量的子层（420,430）（421,431）。 在本发明的一个实施例中，SiGe薄层半导体结构包含在电介质层（610）上具有介电层（610），含Si种子层（615）的半导体衬底（600），可变组合物SixGe1- x2层（620）上，以及位于可变组成SixGe 1-x层（620）上的Si覆盖层（630）。 还提供了一种用于制造SiGe薄层半导体结构的方法和处理工具（100）。

公开(公告)号：WO2005095666A2

公开(公告)日：2005-10-13

申请号：PCT/US2005/001584

申请日：2005-01-20

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  VUKOVIC, Miro ,  RUSSEL, Derek, Andrew

Inventor： VUKOVIC, Miro ,  RUSSEL, Derek, Andrew

IPC: C23C14/00

CPC classification number: H01J37/3405 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/32532 ,  H01J37/3266 ,  H01J37/32724 ,  H01J37/3414 ,  H01J37/3461 ,  H01J37/3497 ,  H01J2237/332

Abstract: A capacitive plasma source (22) for iPVD is immersed in a strong local magnetic field (31), and may be a drop-in replacement for an inductively coupled plasma (ICP) source of iPVD. The source includes an annular electrode (23) having a magnet pack (90) behind it that includes a surface magnet (33-35) generally parallel to the electrode surface with a magnetic field extending radially over the electrode surface. Side magnets, such as inner and outer annular ring magnets (36 and 32, respectively), have polar axes that intersect the electrode with poles closest to the electrode of the same polarity as the adjacent pole of the surface magnet. A ferromagnetic back plate (37) or back magnet (37a) interconnects the back poles of the side magnets (32, 36). A ferromagnetic shield (37b) behind the magnet pack (30) confines the field away (31) from the iPVD material source (21).

Abstract translation: 用于iPVD的电容等离子体源（22）浸入强的局部磁场（31）中，并且可以替代iPVD的电感耦合等离子体（ICP）源。 源包括环形电极（23），该环形电极（23）在其后面具有磁体组件（90），其包括大致平行于电极表面的表面磁体（33-35），其中磁场沿电极表面径向延伸。 诸如内外环形磁铁（分别为36和32）的侧磁体具有与电极相交的极轴，极极与最靠近与表面磁体的相邻磁极相同极性的电极。 铁磁背板（37）或后磁铁（37a）将侧磁体（32,36）的后极互连。 磁体组件（30）后面的铁磁屏蔽（37b）限制了与iPVD材料源（21）的距离（31）。

公开(公告)号：WO2005067006A1

公开(公告)日：2005-07-21

申请号：PCT/US2004/041111

申请日：2004-12-08

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  KAUSHAL, Sanjeev ,  SUGISHIMA, Kenji ,  PANDEY, Pradeep

Inventor： KAUSHAL, Sanjeev ,  SUGISHIMA, Kenji ,  PANDEY, Pradeep

IPC: H01L21/00

CPC classification number: H01L21/67248

Abstract: Methods for adaptive real time control of a system for thermal processing substrates, such as semiconductor wafers and display panels. Generally, the method includes creating a dynamic model (904) of the thermal processing system (900), incorporating wafer bow in the dynamic model (904), coupling a diffusion-­amplification model into the dynamic thermal model (904), creating a multivariable controller (922), parameterizing the nominal setpoints, creating a process sensitivity matrix, creating intelligent setpoints using an efficient optimization method and process data, and establishing recipes that select appropriate models and setpoints during run­time.

Abstract translation: 用于热处理衬底（例如半导体晶片和显示面板）的系统的自适应实时控制的方法。 通常，该方法包括创建热处理系统（900）的动态模型（904），其中将动态模型（904）中的晶片弓结合，将扩散扩增模型耦合到动态热模型（904）中，创建多变量 控制器（922），参数化标称设定值，创建过程灵敏度矩阵，使用有效的优化方法和过程数据创建智能设定值，以及建立在运行时期间选择合适的模型和设定值的配方。

公开(公告)号：WO2005034210A1

公开(公告)日：2005-04-14

申请号：PCT/US2004/032170

申请日：2004-09-30

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  O'MEARA, David, L. ,  BURDETT, Daniel, Craig ,  CABRAL, Stephen, H. ,  LUESINK, Gert ,  KOSTENKO, John, William ,  WAJDA, Cory

Inventor： O'MEARA, David, L. ,  BURDETT, Daniel, Craig ,  CABRAL, Stephen, H. ,  LUESINK, Gert ,  KOSTENKO, John, William ,  WAJDA, Cory

IPC: H01L21/00

CPC classification number: H01L21/67276 ,  B81C99/0065 ,  B81C2201/0138 ,  H01L21/67253

Abstract: A method and system for monitoring status of a system component (200, 300) during a process. The method includes exposing a system component (200, 300) to a reactant gas during a process, where the reactant gas is capable of etching the system component material to form an erosion product, and monitoring release of the erosion product during the process to determine status of the system component (200, 300). Processes that can be monitored include a chamber cleaning process, a chamber conditioning process, a substrate etching process, and a substrate film formation process. The system component (200, 300) can be a consumable system part such as a process tube (25), a shield, a ring, a baffle, an injector, a substrate holder (35, 112), a liner, a pedestal, a cap cover, an electrode, and a heater (15, 20, 65, 70, 122), any of which can further include a protective coating. The processing system (1, 100) includes the system component (200,300) in a process chamber (10, 102), a gas injection system (94, 104) for introducing the reactant gas, a chamber protection system (92, 108) for monitoring the status of the system component (200, 300), and a controller (90, 124) for controlling the processing system (1, 100) in response to the status.

Abstract translation: 一种用于在过程期间监视系统组件（200,300）的状态的方法和系统。 该方法包括在反应气体过程中将系统组分（200,300）暴露于反应气体中，其中反应气体能够蚀刻系统组分材料以形成侵蚀产物，并且在该过程中监测侵蚀产物的释放以确定 系统组件的状态（200,300）。 可以监测的方法包括室清洁过程，室调节过程，基板蚀刻工艺和基板成膜工艺。 系统部件（200,300）可以是消耗系统部件，例如处理管（25），屏蔽件，环形件，挡板，注射器，衬底保持器（35,112），衬垫，基座， 帽盖，电极和加热器（15,20,65,70,122），其中任何一个可进一步包括保护涂层。 处理系统（1,100）包括处理室（10,102）中的系统组件（200,300），用于引入反应气体的气体注入系统（94,104），用于 监视系统组件（200,300）的状态，以及用于响应于该状态控制处理系统（1,100）的控制器（90,124）。

公开(公告)号：WO2005024092A3

公开(公告)日：2005-03-17

申请号：PCT/US2004/025974

申请日：2004-08-12

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  KLESHOCK, Mark ,  FAGUET, Jacques ,  PROVENCHER, Tim

Inventor： KLESHOCK, Mark ,  FAGUET, Jacques ,  PROVENCHER, Tim

IPC: C23C14/35

Abstract: Particle flaking is reduced in a semiconductor wafer processing apparatus (10) by installing a chamber shield assembly (40) in the chamber (11) of the apparatus. The shield assembly includes a plurality of nested shields (41, 42, 43, 44) that are supported out of contact with each other and suspended such that, during thermal expansion and contraction, gaps (52, 56) are maintained that are sufficient to avoid arcing. Alignment structure on the shields and on the chamber walls force the shields to align concentrically and maintain the gaps. The shields are made of aluminum or another thermally conductive material and have cross-sectional areas large enough to provide high thermal conductivity throughout the shields. Mounting flanges (46) and other mounting surfaces are provided on the shields that form intimate thermal contact with sufficient contacting area to insure high thermal conductivity from the shields to the temperature controlled walls (14) of the chamber. Radiant lamps (70) of an array are spaced around the chamber and extend vertically to expose multiple shields across large areas to heat for pre-heating bake-out of the shields and to eliminate thermal shock upon processing the first wafer of a run.

公开(公告)号：WO2012071192A3

公开(公告)日：2012-11-01

申请号：PCT/US2011060381

申请日：2011-11-11

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  DUNN SHANNON W ,  HETZER DAVE

Inventor： DUNN SHANNON W ,  HETZER DAVE

IPC: H01L21/033

CPC classification number: H01L21/0337 ,  G03F7/0035 ,  G03F7/40 ,  G03F7/405 ,  H01L21/0274 ,  Y10S438/947 ,  Y10S438/948 ,  Y10T428/24479 ,  Y10T428/24612

Abstract: A method for patterning a substrate (110, 310) is described. The patterning method may include performing a lithographic process to produce a pattern (122, 142, 321) and a critical dimension (CD) slimming process to reduce a CD (124, 144, 325) in the pattern (122, 142, 321) to a reduced CD (126, 146, 335). Thereafter, the pattern is doubled to produce a double pattern using a sidewall image transfer technique.

Abstract translation: 描述了用于图案化衬底（110,310）的方法。 图案化方法可以包括执行光刻工艺以产生图案（122,142,321）和临界尺寸（CD）减薄工艺以减少图案（122,142,321）中的CD（124,144,325） 到减少的CD（126,146,335）。 之后，使用侧壁图像转印技术将图案加倍以产生双重图案。

公开(公告)号：WO2012061232A3

公开(公告)日：2012-06-28

申请号：PCT/US2011058283

申请日：2011-10-28

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  TAKABA HIROYUKI

Inventor： TAKABA HIROYUKI

IPC: H01L21/20 ,  H01L21/44

CPC classification number: H01L21/02118 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274

Abstract: Embodiments of the invention describe a method for forming dielectric films for semiconductor devices. The method includes providing a substrate in a process chamber containing a microwave plasma source, introducing into the process chamber a non-metal-containing process gas including a deposition gas having a carbon-nitrogen intermolecular bond, forming a plasma from the process gas, and exposing the substrate to the plasma to deposit carbon-nitrogen-containing film on the substrate. In some embodiments, the carbon-nitrogen-containing film can include a CN film, a CNO film, a Si-doped CN film, or a Si-doped CNO film.

Abstract translation: 本发明的实施例描述了一种用于形成用于半导体器件的电介质膜的方法。 该方法包括在包含微波等离子体源的处理室中提供衬底，将包含具有碳 - 氮分子间键的沉积气体的非含金属工艺气体引入处理室，从工艺气体形成等离子体;以及 将衬底暴露于等离子体以在衬底上沉积含碳氮膜。 在一些实施方案中，含碳氮膜可以包括CN膜，CNO膜，掺杂Si的CN膜或Si掺杂的CNO膜。

公开(公告)号：WO2011123433A3

公开(公告)日：2012-03-29

申请号：PCT/US2011030299

申请日：2011-03-29

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  CARCASI MICHAEL A ,  RATHSACK BENJAMIN M ,  SOMERVELL MARK H

Inventor： CARCASI MICHAEL A ,  RATHSACK BENJAMIN M ,  SOMERVELL MARK H

IPC: G03F7/40 ,  G03F7/20 ,  H01L21/67

CPC classification number: G03F7/26 ,  G03F7/2024 ,  G03F7/40 ,  H01L21/67207

Abstract: A method and system for patterning a substrate using a radiation-sensitive material is described. The method (500) and system include forming a layer of radiation-sensitive material on a substrate (510), exposing the layer of radiation- sensitive material to a pattern of radiation (520), and then performing a post-exposure bake following the exposing (530). The imaged layer of radiation-sensitive material is then positive-tone developed to remove a region having high radiation exposure to form radiation-sensitive material lines (540). An exposure gradient within the radiation-sensitive material lines is then removed (550), followed by slimming the radiation-sensitive material lines (560).

Abstract translation: 描述了使用辐射敏感材料构图衬底的方法和系统。 方法（500）和系统包括在衬底（510）上形成辐射敏感材料层，将辐射敏感材料层暴露于辐射图案（520），然后进行曝光后烘烤 曝光（530）。 然后对成像的辐射敏感材料层进行正色调显影以去除具有高辐射照射的区域以形成辐射敏感材料线（540）。 然后去除辐射敏感材料线内的曝光梯度（550），随后使辐射敏感材料线（560）减薄。