公开(公告)号：KR1020140095182A

公开(公告)日：2014-08-01

申请号：KR1020130007765

申请日：2013-01-24

Applicant: 삼성전자주식회사

Inventor： 김정겸 ,  최정환

IPC: H01L23/48

CPC classification number: H01L25/18 ,  H01L23/49816 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/12044 ,  H01L2924/1301 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A stacked die package comprises a package substrate; a first die mounted on the upper surface of the package substrate; a second die; and an interposer which is mounted on the upper surface of the package substrate and includes a plurality of vertical electrical elements to electrically connect the package substrate and the second die.

Abstract translation: 堆叠的管芯封装包括封装衬底; 安装在所述封装基板的上表面上的第一裸片; 第二个死亡 以及插入器，其安装在封装基板的上表面上并且包括多个垂直电气元件以电连接封装基板和第二管芯。

公开(公告)号：KR1020140086781A

公开(公告)日：2014-07-08

申请号：KR1020130026948

申请日：2013-03-13

Applicant: 삼성전자주식회사

Inventor： 최정환

IPC: G11C5/02 ,  G11C11/40

CPC classification number: H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  G11C5/02 ,  G11C5/063 ,  G11C11/4093 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A memory module according to an embodiment of the present invention includes a plurality of memory devices. Each memory device includes a plurality of memory chips and a buffer chip connected to the memory chips. The memory chips and the buffer chip are stacked, and a first input/output port of the buffer chip is serially connected to an external device. A second input/output port of the buffer chip is connected to an input/output port of each memory chip in parallel. Therefore, the memory module according to the embodiment of the present invention can provide equal latency between ranks. Also, the memory module can reduce capacitive load effect.

Abstract translation: 根据本发明的实施例的存储器模块包括多个存储器件。 每个存储器件包括多个存储器芯片和连接到存储器芯片的缓冲芯片。 存储芯片和缓冲芯片被堆叠，并且缓冲芯片的第一输入/输出端口串联连接到外部设备。 缓冲芯片的第二输入/输出端口并联连接到每个存储芯片的输入/输出端口。 因此，根据本发明的实施例的存储器模块可以在等级之间提供相等的等待时间。 此外，内存模块可以降低容性负载效应。

公开(公告)号：KR1020140073399A

公开(公告)日：2014-06-16

申请号：KR1020130096206

申请日：2013-08-13

Applicant: 삼성전자주식회사

Inventor： 이승운 ,  김영진 ,  박대욱 ,  최정환 ,  김강태

IPC: G06F3/0481 ,  G06F3/14 ,  G06F3/041

CPC classification number: G06F3/04886 ,  G06F3/0481 ,  G06F3/0484 ,  G06F2203/04803 ,  G09G5/14 ,  G09G2340/045 ,  G09G2340/0464 ,  G06F3/041 ,  G06F3/04845 ,  G06F3/0488 ,  G06F3/14 ,  G06F2203/04806

Abstract: Disclosed is a control method of a display device including a touch screen. The control method by the present invention comprises a process of displaying a plurality of windows executing an application while not overlapping each other; a process of displaying a center button disposed on an intersecting point of a plurality of boundary lines dividing the plurality of windows; a step of receiving a window size change command to change the size of one of the plurality of windows; a step of changing the size of at least one of the plurality of windows by corresponding to the window size change command and displaying the window; and a process of enlarging the size of remaining windows and displaying the windows while controlling not to display some windows among the plurality of windows.

Abstract translation: 公开了包括触摸屏的显示装置的控制方法。 本发明的控制方法包括以不重叠的方式显示执行应用程序的多个窗口的处理; 显示设置在划分多个窗口的多个边界线的交叉点上的中心按钮的处理; 接收窗口大小改变命令以改变多个窗口中的一个窗口的大小的步骤; 通过对应于窗口尺寸改变命令来改变多个窗口中的至少一个窗口的尺寸并显示该窗口的步骤; 以及在多个窗口中控制不显示一些窗口的同时扩大剩余窗口的大小并显示窗口的过程。

公开(公告)号：KR1020140071212A

公开(公告)日：2014-06-11

申请号：KR1020130028039

申请日：2013-03-15

Applicant: 삼성전자주식회사

Inventor： 조영철 ,  이정배 ,  최정환

IPC: G06F13/14

Abstract: The present invention relates to an operation method of an input/output (I/O) interface. The operation method of an I/O interface according to an embodiment of the present invention includes the steps of: selecting one among multiple output driver circuits based on a mode selection signal; and outputting a data signal using the selected output driver circuit. The mode selection signal is a control signal used to control an on-die termination (ODT) circuit included in the I/O interface.

Abstract translation: 本发明涉及输入/输出（I / O）接口的操作方法。 根据本发明的实施例的I / O接口的操作方法包括以下步骤：基于模式选择信号在多个输出驱动器电路中选择一个; 并使用所选择的输出驱动器电路输出数据信号。 模式选择信号是用于控制I / O接口中包括的片上终端（ODT）电路的控制信号。

公开(公告)号：KR1020130098039A

公开(公告)日：2013-09-04

申请号：KR1020120019830

申请日：2012-02-27

Applicant: 삼성전자주식회사

Inventor： 김정겸 ,  최정환 ,  현석훈 ,  장성진

IPC: G11C29/04 ,  G11C7/10

CPC classification number: G11C17/18 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C29/04 ,  G11C29/44 ,  G11C29/76 ,  G11C29/78 ,  G11C29/789 ,  G11C2029/4402

Abstract: PURPOSE: A semiconductor device capable of preventing characteristic defects generated after packaging corrects the characteristic defects of a memory device by performing a correction operation to satisfy a timing parameter rule, a refresh rule, an input and output trigger voltage rule, or a data training rule of the memory device. CONSTITUTION: A memory module includes multiple memory devices (110) and a memory buffer (120). The memory device includes an anti-fuse circuit part (112) storing a defective cell address. The anti-fuse circuit part includes an anti-fuse, stores the defective cell address, which is within a memory cell array, in the anti-fuse, and reads the defective cell address out to the outside. The anti-fuse circuit part stores a defective cell address generated in a test process of the memory device. The anti-fuse circuit part stores a defective cell address generated after the memory device is packaged.

Abstract translation: 目的：能够防止包装后产生的特征缺陷的半导体装置通过执行定时参数规则，刷新规则，输入和输出触发电压规则或数据训练规则的校正操作来校正存储器件的特征缺陷 的存储器件。 构成：存储器模块包括多个存储器件（110）和存储器缓冲器（120）。 存储器件包括存储有缺陷单元地址的反熔丝电路部分（112）。 反熔丝电路部分包括反熔丝，将存储单元阵列内的有缺陷单元地址存储在反熔丝中，并将缺陷单元地址读出到外部。 反熔丝电路部分存储在存储器件的测试过程中产生的有缺陷的单元地址。 反熔丝电路部分存储在存储器件被封装之后产生的有缺陷的单元地址。

公开(公告)号：KR1020130031650A

公开(公告)日：2013-03-29

申请号：KR1020110095354

申请日：2011-09-21

Applicant: 삼성전자주식회사

Inventor： 송인달 ,  최정환 ,  양윤석

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1057 ,  G11C7/1084 ,  H03K19/0005 ,  G11C7/10 ,  G11C7/22

Abstract: PURPOSE: A method and apparatus for operating a memory device are provided to issue a command according to the level of a control signal inputted through a control pin. CONSTITUTION: ODT signals(ODT0,ODT2,ODT3,ODT3) are received through an ODT pin. A command is issued or an ODT circuit is controlled. The resistance of the final resistor in the ODT circuit is changed or the ODT circuit is turned on or off. The command is issued in response to the ODT signal when the level of the ODT signal is toggled at each edge of a clock signal.

Abstract translation: 目的：提供一种用于操作存储器件的方法和装置，以根据通过控制引脚输入的控制信号的电平发出命令。 构成：通过ODT引脚接收ODT信号（ODT0，ODT2，ODT3，ODT3）。 发出命令或控制ODT电路。 ODT电路中的最终电阻的电阻发生变化，或者ODT电路导通或关断。 当在时钟信号的每个边缘切换ODT信号的电平时，响应于ODT信号发出该命令。

公开(公告)号：KR1020120113976A

公开(公告)日：2012-10-16

申请号：KR1020110031685

申请日：2011-04-06

Applicant: 삼성전자주식회사

Inventor： 고가람 ,  최정환 ,  김인규 ,  서희

IPC: H04L12/24 ,  H04W4/12 ,  G06F15/16

CPC classification number: H04L67/26 ,  H04L67/10 ,  H04W4/00 ,  H04W8/22 ,  H04W88/02

Abstract: PURPOSE: A server cluster and a method thereof for a push-alarm service are provided to reduce a load of a management server cluster by dividing the management server cluster and a push server. CONSTITUTION: One or more push servers include a first push server. If there is a push alarm event, the first push server transfers event information about the generated push alarm event to a mobile terminal. If a connection to a push server is requested, a management server cluster(120) searches for the first push server corresponding to a preset search standard. The management server cluster supplies connection information to the mobile terminal. [Reference numerals] (100) Push alarm server cluster; (110) Transfer server cluster; (120) Management server cluster; (130) First push server; (140) Second push server; (150) N-th push server; (200) Push alarm providing server; (300) Mobile terminal

Abstract translation: 目的：提供用于推送报警服务的服务器集群及其方法，以通过划分管理服务器集群和推送服务器来减少管理服务器集群的负载。 构成：一个或多个推送服务器包括第一个推送服务器。 如果存在推送报警事件，则第一推送服务器将关于生成的推送报警事件的事件信息传送到移动终端。 如果请求与推送服务器的连接，则管理服务器集群（120）搜索对应于预设搜索标准的第一推送服务器。 管理服务器集群向移动终端提供连接信息。 （附图标记）（100）推送报警服务器集群; （110）传输服务器集群; （120）管理服务器集群; （130）第一推送服务器; （140）第二推送服务器; （150）N推送服务器; （200）推送报警提供服务器; （300）移动终端

公开(公告)号：KR101171015B1

公开(公告)日：2012-08-08

申请号：KR1020060010824

申请日：2006-02-03

Applicant: 삼성전자주식회사

Inventor： 최정환 ,  송인상 ,  권상욱 ,  김동균

IPC: G01S13/08

CPC classification number: G01S7/282 ,  G01S13/10 ,  H03K3/86

Abstract: 기계적 스위치를 이용하여 신호를 안정적으로 변조할 수 있는 신호 변환 장치 및 이를 구비한 위치 인식 시스템이 개시된다. 신호 변환 장치는 인가되는 동기 신호에 응답하여 예비 펄스 신호를 생성하는 신호 생성부, 예비 펄스 신호를 가변하여 소정 펄스 폭을 갖는 펄스 신호들로 변환하는 제어 신호들을 출력하는 신호 제어부 및 제어 신호들에 응답하여 예비 펄스 신호를 서로 다른 펄스 폭을 갖는 펄스 신호들로 변환하는 신호 변조부를 포함한다. 신호 변조부는 복수개의 기계적 스위치가 병렬로 연결된 스위치 뱅크 및 각 기계적 스위치가 형성된 노드 사이의 전송 선로를 포함한다. 기계적 스위치를 이용하여 신호 변조부를 형성함으로써 신호의 안정적인 변조와 제품의 소형화 및 저 소모 전력화를 도모할 수 있다.
펄스, 변조, MEMS, 타겟 위치

公开(公告)号：KR1020120067136A

公开(公告)日：2012-06-25

申请号：KR1020100128582

申请日：2010-12-15

Applicant: 삼성전자주식회사

Inventor： 최정환

IPC: G06F13/14 ,  G06F9/06

CPC classification number: G06F17/30117

Abstract: PURPOSE: An electronic device and a method for preventing the deletion of files for the device are provided to determine whether a filter is deleted by using a deletion preventing region. CONSTITUTION: An interfacing part(150) is in connection with a computer. A storing part(140) stores files based on a file allocation table file system with a deletion preventive region. If a command for deleting at least one file stored in the storing part, a controlling part(160) determines whether the file is deleted by using the deletion preventive region. The deletion preventive region is a separated deletion preventive file allocation table region.

Abstract translation: 目的：提供用于防止删除设备文件的电子设备和方法，以通过使用删除防止区域来确定是否删除过滤器。 构成：接口部分（150）与计算机连接。 存储部（140）基于具有删除预防区域的文件分配表文件系统存储文件。 如果用于删除存储在存储部分中的至少一个文件的命令，则控制部分（160）通过使用删除预防区域来确定文件是否被删除。 删除预防区域是分离的删除预防文件分配表区域。

公开(公告)号：KR1020110080406A

公开(公告)日：2011-07-13

申请号：KR1020100000603

申请日：2010-01-05

Applicant: 삼성전자주식회사

Inventor： 최정환

IPC: G11C11/407 ,  G11C8/00 ,  G11C11/4076 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  H03L7/081

CPC classification number: G11C8/00 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  H03L7/07 ,  H03L7/08 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  G11C11/407

Abstract: PURPOSE: A delay-locked-loop circuit, and a semiconductor device and a memory system including the same are provided to shorten time required for synchronizing an internal clock signal to an external clock signal in case of the change of the clock signal. CONSTITUTION: A delay-locked-loop circuit(1000) includes a first delay-locked-loop(1100) and a second delay-locked-loop(1300). The first delay-locked-loop generates a first internal clock signal, which is synchronized with an external clock signal by controlling the delayed amount of the external clock signal, when an external clock signal includes low frequency. The second delay-locked-loop generates a second internal clock signal, which is synchronized with the external clock signal by controlling the delayed amount of the external clock signal, when the external clock signal includes high frequency.

Abstract translation: 目的：提供延迟锁定环电路，以及包括该延迟锁定环电路的半导体器件和存储器系统，以在时钟信号改变的情况下缩短将内部时钟信号与外部时钟信号同步所需的时间。 构成：延迟锁定环电路（1000）包括第一延迟锁定环（1100）和第二延迟锁定环（1300）。 当外部时钟信号包括低频时，第一延迟锁定环产生第一内部时钟信号，其通过控制外部时钟信号的延迟量与外部时钟信号同步。 第二延迟锁定环产生第二内部时钟信号，当外部时钟信号包括高频时，通过控制外部时钟信号的延迟量与外部时钟信号同步。