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公开(公告)号：KR1020150077785A
公开(公告)日：2015-07-08
申请号：KR1020130166622
申请日：2013-12-30
Applicant: 삼성전자주식회사
IPC: G11C5/14
CPC classification number: G06F1/3275 , G06F1/3225 , G11C7/1054 , G11C7/1081 , Y02D10/14
Abstract: 메모리시스템은메모리콘트롤러, 메모리장치및 채널을포함한다. 메모리콘트롤러와메모리장치는적어도하나의광 신호선을포함하는채널을통하여연결된다. 메모리장치는광 신호선상의적어도하나의광 신호와메모리장치의적어도하나의내부전기신호상호간을변환하는제1 변환부및 메모리장치의동작상태에기초하여제1 변환부의전력소모량을조절하는제1 전력제어부를포함한다.
Abstract translation: 存储器系统包括存储器控制器，存储器件和通道。 存储器控制器和存储器件通过包括至少一个光信号线的通道连接。 存储装置包括：第一转换单元，其执行光信号线上的至少一个光信号与存储器件的至少一个内部电信号之间的转换;以及第一功率控制单元，其控制第一转换的功耗 基于存储器件的操作状态的单元。
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公开(公告)号：KR1020150060423A
公开(公告)日：2015-06-03
申请号：KR1020130144819
申请日：2013-11-26
Applicant: 삼성전자주식회사
CPC classification number: H04B10/572 , H04B10/506 , H04B10/671 , H04B10/801 , H04J14/0278
Abstract: 광전송변환장치는파장선택기, 광전변환기및 전광변환기를포함한다. 파장선택기는파장제어신호에응답하여수신파장선택신호및 송신파장선택신호를제공한다. 광전변환기는메모리컨트롤러로부터전송되는수신광 신호및 수신파장선택신호에기초하여적어도하나의수신선택파장에상응하는선택광 신호를수신전기신호로변환한다. 전광변환기는송신파장선택신호및 메모리컨트롤러로전송되는송신전기신호에기초하여송신전기신호를적어도하나의송신선택파장에상응하는송신광 신호로변환한다. 광전송변환장치는메모리시스템의데이터전송속도를증가시킬수 있고, 광전송변환장치를포함하는옵티컬디바이스의생산효율성을높일수 있다.
Abstract translation: 光传输转换器包括波长选择器，光电转换器和电光转换器。 波长选择器响应波长控制信号提供接收波长选择信号和传输波长选择信号。 光电转换器基于从存储器控制器发送的接收波长选择信号和接收光信号，将对应于至少一个接收选择波长的选择光信号转换为接收电信号。 电光转换器基于发送到存储器控制器的传输电信号和传输波长选择信号，将传输电信号转换成对应于至少一个传输选择波长的传输光信号。 光传输转换器提高了存储系统的数据传输速度。 提高了包括光传输转换器的光学装置的生产效率。
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公开(公告)号：KR1020140112818A
公开(公告)日：2014-09-24
申请号：KR1020130027383
申请日：2013-03-14
Applicant: 삼성전자주식회사
IPC: H01L25/065 , H01L25/07
CPC classification number: G11C5/063 , G11C5/025 , H01L25/0657 , H01L2224/16146 , H01L2225/06513 , H01L2225/06517 , H01L2225/06534 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2224/13099
Abstract: A memory chip package according to the present invention includes memory chips of a stacked structure. The memory chips input/output an optical signal through an optical line having a via which penetrates the memory chips electrically connected to each other. The memory chips input/output optical signals of different wavelengths, respectively. The memory chips include a photoelectric converter, respectively, receive the optical signals of corresponding wavelengths, convert them into electric signals or receive electric signals and convert them into optical signals of corresponding wavelengths.
Abstract translation: 根据本发明的存储芯片封装包括堆叠结构的存储芯片。 存储器芯片通过具有穿过彼此电连接的存储器芯片的通孔的光线输入/输出光信号。 存储芯片分别输入/输出不同波长的光信号。 存储芯片包括光电转换器，分别接收相应波长的光信号，将其转换为电信号或接收电信号并将其转换成相应波长的光信号。
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公开(公告)号：KR1020140112865A
公开(公告)日：2014-09-24
申请号：KR1020130027495
申请日：2013-03-14
Applicant: 삼성전자주식회사
IPC: G11C11/42
CPC classification number: H04B10/2575 , H04B10/801
Abstract: According to an embodiment of the present invention, an electric optical memory system comprises a semiconductor memory device receiving a first electric signal and storing data; a memory controller generating a second electric signal to control the semiconductor memory device; an electric to optical converter which receives the second electric signal from the memory controller, converts the second electric signal into a second optical signal and is connected to the exterior of the memory controller; and an optical to electric converter which receives the first optical signal from the electric to optical converter and converts the first electric signal.
Abstract translation: 根据本发明的实施例，电光存储系统包括接收第一电信号并存储数据的半导体存储器件; 产生第二电信号以控制半导体存储器件的存储器控制器; 从存储器控制器接收第二电信号的电光转换器将第二电信号转换为第二光信号并连接到存储器控制器的外部; 以及光电转换器，其从电光转换器接收第一光信号并转换第一电信号。
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Patent Agency Ranking
公开(公告)号：KR1020130107841A
公开(公告)日：2013-10-02
申请号：KR1020120029964
申请日：2012-03-23
Applicant: 삼성전자주식회사
CPC classification number: G06F13/1663
Abstract: PURPOSE: A memory system stably and efficiently expands memory capacity by using a point-to-point method. CONSTITUTION: A first memory module (200) is directly connected to a memory controller through a first memory bus and exchanges first data with the memory controller through the first memory bus. A second memory module (300) exchanges second data with the memory controller through a second memory bus. A third memory module (400) exchanges the first data with the memory controller through the first and third memory buses. A fourth memory module (500) exchanges the second data with the memory controller through the second and fourth memory buses.
Abstract translation: 目的：通过使用点对点方法，可以稳定有效地扩展存储容量。 构成：第一存储器模块（200）通过第一存储器总线直接连接到存储器控制器，并通过第一存储器总线与存储器控制器交换第一数据。 第二存储器模块（300）通过第二存储器总线与存储器控制器交换第二数据。 第三存储器模块（400）通过第一和第三存储器总线与存储器控制器交换第一数据。 第四存储器模块（500）通过第二和第四存储器总线与存储器控制器交换第二数据。
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公开(公告)号：KR1020140095182A
公开(公告)日：2014-08-01
申请号：KR1020130007765
申请日：2013-01-24
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L25/18 , H01L23/49816 , H01L25/0652 , H01L25/0657 , H01L2224/16225 , H01L2225/06517 , H01L2225/06527 , H01L2225/06562 , H01L2924/12044 , H01L2924/1301 , H01L2924/15311 , H01L2924/00
Abstract: A stacked die package comprises a package substrate; a first die mounted on the upper surface of the package substrate; a second die; and an interposer which is mounted on the upper surface of the package substrate and includes a plurality of vertical electrical elements to electrically connect the package substrate and the second die.
Abstract translation: 堆叠的管芯封装包括封装衬底; 安装在所述封装基板的上表面上的第一裸片; 第二个死亡 以及插入器，其安装在封装基板的上表面上并且包括多个垂直电气元件以电连接封装基板和第二管芯。
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公开(公告)号：KR1020130098039A
公开(公告)日：2013-09-04
申请号：KR1020120019830
申请日：2012-02-27
Applicant: 삼성전자주식회사
CPC classification number: G11C17/18 , G11C5/04 , G11C11/40 , G11C17/16 , G11C29/04 , G11C29/44 , G11C29/76 , G11C29/78 , G11C29/789 , G11C2029/4402
Abstract: PURPOSE: A semiconductor device capable of preventing characteristic defects generated after packaging corrects the characteristic defects of a memory device by performing a correction operation to satisfy a timing parameter rule, a refresh rule, an input and output trigger voltage rule, or a data training rule of the memory device. CONSTITUTION: A memory module includes multiple memory devices (110) and a memory buffer (120). The memory device includes an anti-fuse circuit part (112) storing a defective cell address. The anti-fuse circuit part includes an anti-fuse, stores the defective cell address, which is within a memory cell array, in the anti-fuse, and reads the defective cell address out to the outside. The anti-fuse circuit part stores a defective cell address generated in a test process of the memory device. The anti-fuse circuit part stores a defective cell address generated after the memory device is packaged.
Abstract translation: 目的：能够防止包装后产生的特征缺陷的半导体装置通过执行定时参数规则，刷新规则，输入和输出触发电压规则或数据训练规则的校正操作来校正存储器件的特征缺陷 的存储器件。 构成：存储器模块包括多个存储器件（110）和存储器缓冲器（120）。 存储器件包括存储有缺陷单元地址的反熔丝电路部分（112）。 反熔丝电路部分包括反熔丝，将存储单元阵列内的有缺陷单元地址存储在反熔丝中，并将缺陷单元地址读出到外部。 反熔丝电路部分存储在存储器件的测试过程中产生的有缺陷的单元地址。 反熔丝电路部分存储在存储器件被封装之后产生的有缺陷的单元地址。
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