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公开(公告)号：KR1020100096917A
公开(公告)日：2010-09-02
申请号：KR1020090016008
申请日：2009-02-25
Applicant: 삼성전자주식회사
IPC: G11C11/407 , G11C8/00 , G11C11/4072
CPC classification number: G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/087 , H03L7/10
Abstract: PURPOSE: A delay lock loop circuit for preventing coarse locking fail is provided to prevent the fail of coarse locking in a delay locked loop frequency domain by controlling a coarse lock window to be suitable for a frequency domain. CONSTITUTION: A delay lock reset(10) generates a reset signal to set the frequency detection section of a delay locked loop(20). The frequency detector(40) generates a plurality of strobe signal by delaying an input frequency signal. The frequency detector output a low check signal indicating a low frequency according to the state of strobe signals which are generated in the first state section. A direct phase detector(30) generates a phase detection pair to vary a coarse lock window while receiving the low check signal.
Abstract translation: 目的：提供一种用于防止粗略锁定失败的延迟锁定环电路，通过控制一个适用于频域的粗略锁窗，防止延迟锁定环频域粗略锁定的失败。 构成：延迟锁定复位（10）产生复位信号，以设置延迟锁定环（20）的频率检测部分。 频率检测器（40）通过延迟输入频率信号来产生多个选通信号。 频率检测器根据在第一状态部分中产生的选通信号的状态输出指示低频的低检查信号。 直接相位检测器（30）产生相位检测对，以在接收到低检查信号的同时改变粗锁窗口。
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公开(公告)号：KR100666177B1
公开(公告)日：2007-01-09
申请号：KR1020050091896
申请日：2005-09-30
Applicant: 삼성전자주식회사
IPC: G06F13/14
CPC classification number: H03K19/017545 , H03K19/017581 , H04L25/0278 , H04L25/0286
Abstract: An output driver for controlling impedance and intensity of a pre-emphasis driver with an MRS(Mode Register Set) is provided to efficiently match output impedance with transmission and reception impedance, and adjust a pre-emphasis time point and range of an output signal. A main driving circuit(100) generates a main signal according to a received data signal to a transfer line(1) with specific main impedance. A sub driving circuit(200) emphasizes the output signal in an early stage of the main signal and generates a sub signal according to the data signal to the transfer line with specific sub impedance. The MRS(300) generates an impedance control signal group controlling a logical state according to an external control signal group. The sub impedance is controlled by the impedance control signal group. The sub driving circuit includes a pre-emphasis driver(210) pulling up the sub signal by responding to a pull-up control signal and a driving control signal generator(230) providing the pull-up/down control signal by responding to the data sign.
Abstract translation: 提供了一种用于控制具有MRS（模式寄存器组）的预加重驱动器的阻抗和强度的输出驱动器，用于有效地匹配输出阻抗与发射和接收阻抗，并调整输出信号的预加重时间点和范围。 主驱动电路（100）根据接收到的数据信号生成具有特定主阻抗的传输线（1）的主信号。 子驱动电路（200）在主信号的早期强调输出信号，并根据具有特定子阻抗的传输线的数据信号生成子信号。 MRS（300）根据外部控制信号组产生控制逻辑状态的阻抗控制信号组。 子阻抗由阻抗控制信号组控制。 子驱动电路包括预加重驱动器（210），通过响应上拉控制信号来提升子信号;以及驱动控制信号发生器（230），通过响应数据提供上拉/下拉控制信号 标志。
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公开(公告)号：KR1020140124202A
公开(公告)日：2014-10-24
申请号：KR1020130041661
申请日：2013-04-16
Applicant: 삼성전자주식회사
IPC: G11C11/4096 , G11C11/4093
CPC classification number: G11C11/4096 , G11C7/1078 , G11C7/22 , G11C11/4076 , G11C11/4093
Abstract: 본 발명은 디램에 구비되는 데이터 입력 회로에 있어서, 디램 작동 조건의 변화를 검출하는 검출부, 검출 결과를 디지털 코드로 변환하는 디지털 코드 생성부, 및 디지털 코드에 따라 신호를 지연시키는 신호 지연부를 포함하는 데이터 입력 회로를 제공한다. 또한 디램의 데이터 입력 방법에 있어서, 디램 상태 측정 단계, 측정된 상태로부터 디램 작동 조건의 변화를 검출하는 단계, 검출 결과를 디지털 코드로 변환하는 단계, 및 디지털 코드에 따라 신호를 지연시키는 단계를 포함하는 데이터 입력 방법을 제공한다. 본 발명은 데이터 신호와 데이터 스트로브 신호의 지연 정도를 유동적으로 조절함으로써, 높은 주파수에서 작동하여 좁은 유효 데이터 구간을 갖는 디램의 오작동을 방지할 수 있게 한다. 즉, 데이터가 디램 작동 조건의 영향을 크게 받지 않고 안정적으로 전송되도록 한다.
Abstract translation: 本发明涉及一种设置在DRAM中的数据输入电路，更具体地说，涉及一种数据输入电路，包括：检测单元，被配置为检测DRAM操作条件的变化;数字码产生单元，被配置为将检测结果转换为 数字码，以及配置成根据数字码延迟信号的信号延迟单元。 此外，本发明涉及一种DRAM的数据输入方法，更具体地说，涉及一种数据输入方法，包括以下步骤：测量DRAM的状态; 从测量状态检测DRAM操作条件的变化; 将检测结果转换成数字代码; 并根据数字代码延迟一个信号。 数据输入电路灵活调整数据信号与数据选通信号之间的延迟程度，以高频工作，从而防止具有窄有效数据部分的DRAM的故障。 也就是说，可以稳定地传输数据，而不受DRAM操作条件的极大影响。
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公开(公告)号：KR1020140112865A
公开(公告)日：2014-09-24
申请号：KR1020130027495
申请日：2013-03-14
Applicant: 삼성전자주식회사
IPC: G11C11/42
CPC classification number: H04B10/2575 , H04B10/801
Abstract: According to an embodiment of the present invention, an electric optical memory system comprises a semiconductor memory device receiving a first electric signal and storing data; a memory controller generating a second electric signal to control the semiconductor memory device; an electric to optical converter which receives the second electric signal from the memory controller, converts the second electric signal into a second optical signal and is connected to the exterior of the memory controller; and an optical to electric converter which receives the first optical signal from the electric to optical converter and converts the first electric signal.
Abstract translation: 根据本发明的实施例，电光存储系统包括接收第一电信号并存储数据的半导体存储器件; 产生第二电信号以控制半导体存储器件的存储器控制器; 从存储器控制器接收第二电信号的电光转换器将第二电信号转换为第二光信号并连接到存储器控制器的外部; 以及光电转换器，其从电光转换器接收第一光信号并转换第一电信号。
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公开(公告)号：KR1020140112663A
公开(公告)日：2014-09-24
申请号：KR1020130026990
申请日：2013-03-14
Applicant: 삼성전자주식회사
CPC classification number: H03L7/0812 , G11C7/222 , H03L7/0818 , H03L7/095
Abstract: A delay locked loop comprises a phase detecting unit which generates first and second phase detecting signals by entering a feedback clock and a first clock; and a coarse lock detecting unit which generates a coarse lock signal by detecting the conversion of the first phase detecting signal and the second phase detecting signal from in-phase to out-of phase. Therefore, the coarse lock fail by the jitter of an input clock can be prevented.
Abstract translation: 延迟锁定环包括相位检测单元，其通过输入反馈时钟和第一时钟来产生第一和第二相位检测信号; 粗锁定检测单元，其通过检测第一相位检测信号和第二相位检测信号从同相到异相的转换来产生粗略锁定信号。 因此，可以防止粗锁由于输入时钟的抖动而失败。
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Patent Agency Ranking
公开(公告)号：KR1020140110234A
公开(公告)日：2014-09-17
申请号：KR1020130024126
申请日：2013-03-06
Applicant: 삼성전자주식회사
CPC classification number: H03K23/42 , H03K23/667
Abstract: Provided are a divided clock generating device and a divided clock generating method. The divided clock generating device includes a chip selection flip flop which generates a chip selection signal synchronized with an internal clock signal, a clock dividing unit which generates a plurality of second divided even/odd clock signals using a first divided clock signal and outputs the internal clock signal, and a clock comparator which selects one of the second divided even/odd clock signals by using the chip selection signal which is synchronized with the internal clock signal. The clock dividing unit divides the internal clock signal by using the first divided clock signal and one selected among the second divided even/odd clock signals according to the selection result of the clock comparator.
Abstract translation: 提供了一种分时钟产生装置和分时钟产生方法。 分割时钟产生装置包括：芯片选择触发器，其生成与内部时钟信号同步的芯片选择信号;时钟分割单元，其使用第一分频时钟信号产生多个第二分频偶数/奇数时钟信号，并输出内部 时钟信号和时钟比较器，其通过使用与内部时钟信号同步的芯片选择信号来选择第二分频偶数/奇数时钟信号之一。 时钟分频单元根据时钟比较器的选择结果，利用第一分频时钟信号和第二分频偶数/奇数时钟信号之一选择内部时钟信号。
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公开(公告)号：KR1020140109209A
公开(公告)日：2014-09-15
申请号：KR1020130047548
申请日：2013-04-29
Applicant: 삼성전자주식회사
CPC classification number: G11C7/222 , G11C7/06 , G11C7/1051 , G11C7/1096 , G11C2207/2272
Abstract: A memory device is provided. The memory device comprises n-1 frequency demultipliers which create a second demultiply clock or n (n is a natural number satisfying a following equation, n>=2) clocks by demultiplying a first clock; a first delay unit which creates a first demultiply clock which delays the first lock for the same time applied to the second demultiply clock or the n multiply clock for delaying; an MUX unit which receives the first demultiply clock or the n multiply clock and chooses one of the clocks; a flip-flop unit which is connected to the MUX unit, receives and synchronizes the selected demultiply clock and a first signal; and a command decoder unit which decodes the synchronized signal provided from the flip-flop unit and creates internal command signal.
Abstract translation: 提供存储器件。 存储器件包括n-1个分频器，其通过解除第一时钟而产生第二解复用时钟或n（n是满足以下等式的自然数，n> = 2）个时钟; 第一延迟单元，其创建第一多分支时钟，其延迟施加到第二解复用时钟的相同时间的第一锁定或用于延迟的n个乘法时钟; MUX单元，其接收第一多分钟时钟或n个乘法时钟并选择其中一个时钟; 连接到MUX单元的触发器单元接收并同步所选择的多分数时钟和第一信号; 以及命令解码器单元，其对从触发器单元提供的同步信号进行解码并产生内部命令信号。
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公开(公告)号：KR101551774B1
公开(公告)日：2015-09-10
申请号：KR1020090016008
申请日：2009-02-25
Applicant: 삼성전자주식회사
IPC: G11C11/407 , G11C8/00 , G11C11/4072
CPC classification number: G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/087 , H03L7/10
Abstract: 지연고정루프의록킹동작시 코아스록킹페일을방지또는최소화하기위한지연고정루프회로가개시된다. 그러한지연고정루프회로는, 지연고정루프와; 상기지연고정루프의주파수검출구간을설정하기위한리셋신호를생성하는딜레이록 리셋부와; 입력주파수신호를지연하여복수개의스트로브신호들을생성하고그 생성된스트로브신호들이상기입력주파수신호의제1 상태구간내에서모두위치되어지는경우에로우주파수임을가리키는로우체크신호를출력하는주파수검출기와; 상기주파수검출기의상기로우체크신호를수신할경우에코아스록 윈도우를가변하기위한위상검출페어를생성하는다이렉트위상검출기를구비한다. 상기한구성에따르면, 코아스록 윈도우가주파수대역에맞게조절되어지므로, 지연고정루프주파수영역에서코아스록킹페일이방지되고개선된회로성능이얻어진다.
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公开(公告)号：KR1020140081288A
公开(公告)日：2014-07-01
申请号：KR1020120150872
申请日：2012-12-21
Applicant: 삼성전자주식회사
IPC: G11C11/4063 , G11C11/4076
CPC classification number: G06F1/12 , G11C5/144 , G11C5/148 , G11C7/225 , G11C11/4076 , G11C2207/2227
Abstract: Provided are a command control circuit for a memory device and the memory device including the same. The command control circuit for the memory device includes a command decoder which generates an internal command signal by using a command signal and a chip selection (CS) signal and a CS gating logic which supplies the CS signal to the command decoder. When a clock enable (CKE) signal is a first level, the CS gating logic supplies the CS signal to the command decoder. When the CKE signal is a second level, the CS gating logic blocks the CS signal in the command decoder.
Abstract translation: 提供了一种用于存储器件的命令控制电路和包括其的存储器件。 用于存储器件的命令控制电路包括通过使用命令信号和片选（CS）信号产生内部命令信号的命令解码器和将CS信号提供给命令解码器的CS门控逻辑。 当时钟使能（CKE）信号为第一电平时，CS门控逻辑将CS信号提供给命令解码器。 当CKE信号为第二电平时，CS门控逻辑封锁命令解码器中的CS信号。
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