公开(公告)号：WO1998002838A1

公开(公告)日：1998-01-22

申请号：PCT/US1997012069

申请日：1997-07-11

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  NESTLER, Eric

IPC: G06J01/00

CPC classification number: G06J1/00

Abstract: An apparatus and a method for multiplying two time varying signals to produce a four quadrant, multiplied signal is provided. In one embodiment of the present invention, an apparatus for multiplying a first signal with a second signal includes an analog-to-digital converter that provides a first digital signal representative of the first signal, a first modulator that provides a first modulated signal representative of the second signal, a multiplier that multiplies that first digital signal by the first modulated signal and provides a second digital signal representative of a result of a multiplication of the first signal and the second signal, and a first filter having an input to receive the second digital signal and having an output that provides the multiplied signal.

Abstract translation: 提供了一种用于将两个时变信号相乘以产生四象限乘法信号的装置和方法。 在本发明的一个实施例中，一种用于将第一信号与第二信号相乘的装置包括提供表示第一信号的第一数字信号的模数转换器，提供表示第一信号的第一调制信号的第一调制器 所述第二信号是将所述第一数字信号乘以所述第一调制信号并提供代表所述第一信号和所述第二信号的相乘结果的第二数字信号的乘法器，以及具有用于接收所述第二信号的输入的第一滤波器 数字信号并具有提供相乘信号的输出。

公开(公告)号：WO1997004456A1

公开(公告)日：1997-02-06

申请号：PCT/US1996011752

申请日：1996-07-16

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  PENCHUK, Robert, A.

IPC: G11C07/06

CPC classification number: G11C7/062

Abstract: A sense amplifier for determining the state of a memory cell of a random access memory includes first and second transistors connected in a differential amplifier configuration. The first and second transistors have control electrodes coupled to Bit and Bit B lines, respectively, for sensing a state of the memory cell. The sense amplifier further includes third and fourth transistors connected in a differential amplifier configuration. The differential amplifier configuration has an offset error and provides differential outputs for indicating the state of the memory cell during a read phase. The sense amplifier further includes first and second capacitors respectively coupled between the control electrodes of the third and fourth transistors and a reference potential, and a feedback circuit for coupling voltages representative of the offset error to the first and second capacitors during a nulling phase in which the Bit and Bit B lines are not being read. The first and third transistors may be connected in series or in parallel. Similarly, the second and fourth transistors may be connected in series or in parallel. By nulling offset error, the access time of the RAM is reduced.

Abstract translation: 用于确定随机存取存储器的存储单元的状态的读出放大器包括以差分放大器配置连接的第一和第二晶体管。 第一和第二晶体管分别具有耦合到位和位B线的控制电极，用于感测存储单元的状态。 读出放大器还包括以差分放大器配置连接的第三和第四晶体管。 差分放大器配置具有偏移误差，并提供用于在读取阶段期间指示存储器单元的状态的差分输出。 感测放大器还包括分别耦合在第三和第四晶体管的控制电极和参考电位之间的第一和第二电容器，以及反馈电路，用于将代表偏移误差的电压耦合到第一和第二电容器， 位和位B线未被读取。 第一和第三晶体管可以串联或并联连接。 类似地，第二和第四晶体管可以串联或并联连接。 通过归零偏移误差，RAM的访问时间减少。

公开(公告)号：WO1996041248A1

公开(公告)日：1996-12-19

申请号：PCT/US1996009348

申请日：1996-06-05

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MIRANDA, Evaldo, M. ,  BROOKS, Todd ,  BROKAW, A., Paul

IPC: G05F01/565

CPC classification number: G05F1/565

Abstract: A low drop-out voltage regulator is compensated by providing a compensation capacitor across an output terminal of the regulator and an output lead of an input stage which compares a reference voltage and a voltage derived from a regulated output signal at the output terminal. The output from the input stage is inverted without gain before being provided to an output stage. This inversion allows Miller compensation with the compensation capacitor.

Abstract translation: 通过在调节器的输出端子和输入级的输出引线之间提供补偿电容器来补偿低压差稳压器，该输入级比较输出端子上的参考电压和从稳压输出信号导出的电压。 在提供给输出级之前，输入级的输出无增益地反相。 该反转允许使用补偿电容器进行米勒补偿。

公开(公告)号：WO1996039615A1

公开(公告)日：1996-12-12

申请号：PCT/US1996008985

申请日：1996-06-03

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GEEN, John, A.

IPC: G01C19/56

CPC classification number: G01C19/5712 ,  G01P15/18 ,  H02N1/008

Abstract: A micromachined device has a plurality of rotationally dithered masses (10, 12) that are used to sense acceleration. To eliminate common modes, the masses are dithered in an equal and opposite manner. To help maintain this relationship between the movement of the masses, a coupling fork (60) provides minimal resistance to anti-phase movement and substantial resistance to in-phase movement. Electrodes (50) are used to detect changes in capacitance between the masses and the substrate resulting from rotation of the device about a radial axis of a mass. These electrodes are electrically connected to eliminate gradients that are caused by external forces and manufacturing differences. Four masses (100a-100d) or more can be provided, arranged in a two-dimensional array, such as a square or hexagon with a coupling fork (102) provided between each pair of masses, and with electrodes (104-107) connected to eliminate gradients.

Abstract translation: 微加工装置具有用于感测加速度的多个旋转抖动质量块（10,12）。 为了消除共同的模式，群众以相同和相反的方式颤抖。 为了保持质量运动之间的这种关系，联结叉（60）提供最小的抵抗反相运动的阻力和对同步运动的实质阻力。 电极（50）用于检测由器件围绕质量的径向轴旋转而产生的质量和基体之间的电容变化。 这些电极电连接以消除由外力和制造差异引起的梯度。 可以提供四个质量（100a-100d）或更多，其布置成二维阵列，例如正方形或六边形，在每对质量之间设置有耦合叉（102），并且连接电极（104-107） 消除梯度。

公开(公告)号：WO1996034292A1

公开(公告)日：1996-10-31

申请号：PCT/US1996004751

申请日：1996-04-08

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  JORDAN, Edward, Perry

IPC: G01R01/02

CPC classification number: H03K4/08 ,  H03K6/00

Abstract: A calibration system for an asymmetrical ramp generator for a pulse width modulator includes a complementary clock circuit (152); a first symmetrical dual ramp generator (156) for generating first and second ramps; a comparator device (158, 160) for generating first and second asymmetrical drive signals; a second asymmetrical dual ramp generator (162, 164) for generating third and fourth asymmetrical overlapping ramps; a calibration circuit (304); a first current splitting circuit (176) for establishing a reference level; a second current splitting circuit (176) for providing slew rate currents to the first (156) and second (162, 164) ramp generators for controlling the slew rate of the ramps; a current stepping device (320) for varying the current to the second current splitting circuit; the calibration circuit (304) including means (332) for fixing the current provided by the current stepping device (320) to the first and second ramps, simultaneously calibrating the third and fourth ramps, stopping the calibration, and returning the reference level to within the predetermined voltage range.

Abstract translation: 用于脉冲宽度调制器的非对称斜坡发生器的校准系统包括互补时钟电路（152）; 用于产生第一和第二斜坡的第一对称双斜坡发生器（156）; 用于产生第一和第二不对称驱动信号的比较器装置（158,160）; 用于产生第三和第四不对称重叠斜面的第二不对称双斜坡发生器（162,164）; 校准电路（304）; 用于建立参考电平的第一电流分流电路（176） 用于向第一（156）和第二（162,164）斜坡发生器提供转换速率电流的第二电流分流电路（176），用于控制斜坡的转换速率; 用于改变到第二分流电路的电流的电流步进装置（320）; 校准电路（304）包括用于将由当前步进装置（320）提供的电流固定到第一和第二斜坡的装置（332），同时校准第三和第四斜坡，停止校准，并将参考电平返回到内 预定电压范围。

公开(公告)号：WO1996025798A3

公开(公告)日：1996-08-22

申请号：PCT/US1996002056

申请日：1996-02-15

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  COTTER, Martin, G. ,  GARAVAN, Patrick, J.

IPC: H03M01/38

公开(公告)号：WO1996017438A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015540

申请日：1995-11-30

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  DEEVY, Kenneth, T. ,  QUINLAN, Philip

IPC: H03M07/22

CPC classification number: H03M7/165

Abstract: A MOS ROM architecture which is fast-switching, requires almost no current under static conditions and only small current while switching, does not require a precharge mechanism and exhibits high immunity to electrical noise. A flash converter using this ROM architecture has a "one of" circuit driving a ROM encoder stage. The ROM constitutes a "one of" to Gray- or modified Gray code encoder, or a "one-of" to binary encoder. Each bit cell in the ROM has a single NMOS transistor with its drain connected to either zero volts (representing logical 0) or to a VDD supply of, for example, 5 volts (representing logical 1). The transistor's source is connected to the bit line. All bit cell transistor gates for a given ROM address (i.e., location) are driven in parallel by an enable/disable signal. Preferably, the N-channel transistors whose drains are connected to logical 0 are about twice as large as those whose drains are connected to logical 1, to achieve desirable drain-to-source "on" resistance, Ron, and obtain a "low" output voltage when sparkle codes occur. Each bit line is connected to a buffer inverter whose trigger point is scaled to operate with a bit line that can only swing as high as VDD-VT (i.e., one threshold voltage below the supply voltage, VDD) when the bit line is connected to a logical 1. There is high noise immunity because the bit lines are always driven and do not float at high impedance. Static current is drawn only when there is a thermometer code bubble, causing bit cell transistors to contend for control of a bit line. Otherwise, current is needed only during switching.

Abstract translation: 快速切换的MOS ROM架构在静态条件下几乎不需要电流，而在切换时只需要小的电流，不需要预充电机制并且对电噪声具有很高的抗扰性。 使用这种ROM架构的闪存转换器具有驱动ROM编码器级的“一个”电路。 ROM构成了格雷码或格雷码编码器的“一个”，或者是二进制编码器的“一”。 ROM中的每个位单元具有单个NMOS晶体管，其漏极连接到零伏（表示逻辑0）或VDD电源，例如5伏（表示逻辑1）。 晶体管的源极连接到位线。 用于给定ROM地址（即，位置）的所有位单元晶体管栅极通过使能/禁止信号并行驱动。 优选地，其漏极连接到逻辑0的N沟道晶体管的大约是其漏极连接到逻辑1的N沟道晶体管，以实现期望的漏极到源极“导通”电阻Ron，并获得“低” 输出电压时出现闪烁码。 每个位线连接到一个缓冲逆变器，其触发点被缩放以便在位线连接到位线时仅能够像VDD-VT（即，一个阈值电压低于电源电压VDD）摆动的位线工作。 逻辑1.具有高抗噪性，因为位线总是被驱动，并且不会在高阻抗下浮动。 只有当有温度计代码气泡时才产生静态电流，导致位单元晶体管竞争控制位线。 否则，仅在切换期间需要电流。

公开(公告)号：WO1996017437A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015467

申请日：1995-11-29

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MURDEN, Frank ,  MORELAND, Carl, W.

IPC: H03M01/44

CPC classification number: H03F3/26 ,  H03F3/45103 ,  H03F3/45107 ,  H03F2203/45302 ,  H03F2203/45311 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45371 ,  H03F2203/45702 ,  H03F2203/45722 ,  H03M1/445

Abstract: A serial-type A/D converter that uses magnitude amplifiers ("magamps") and comparators for effecting the conversion of analog signals to Gray scale code signals that are then converted to binary digital signals by a Gray scale code-to-binary portion of the serial-type A/D converter. More specifically, a serial-type A/D converter that uses an n-bit converter that has n-1 magamps and n-comparators. The n-1 magamps are cascaded such that the VOL and VOH outputs of a stage is the inputs to the next stage. The output of the comparators are input to the Gray scale code-to-binary portion of the serial A/D converter. The latching of the comparators occurs outside of the magamps. This allows for the parallel latching of the n comparators. The speed of the serial-type A/D converter is determined by the bandwidth of the magamps. The serial-type A/D converter includes an offset method that significantly reduces the effects of early voltage, VA, on the output waveforms. Each stage of the serial-type A/D converter may have any desired gain and not limited to a particular gain.

Abstract translation: 一种使用幅度放大器（“magamps”）和比较器的串行型A / D转换器，用于将模拟信号转换为灰度代码信号，然后通过灰度代码到二进制部分转换为二进制数字信号 串行型A / D转换器。 更具体地，是使用具有n-1个magamp和n比较器的n位转换器的串行型A / D转换器。 级联的n-1型卡子使得一级的VOL和VOH输出是下一级的输入。 比较器的输出被输入到串行A / D转换器的灰度代码到二进制部分。 比较器的锁存发生在卡盘之外。 这允许n个比较器的并联闭锁。 串行型A / D转换器的速度由卡盘的带宽决定。 串行型A / D转换器包括一种偏移方法，可显着降低早期电压VA对输出波形的影响。 串行型A / D转换器的每个级可以具有任何期望的增益，而不限于特定的增益。

公开(公告)号：WO1996016482A1

公开(公告)日：1996-05-30

申请号：PCT/US1995015164

申请日：1995-11-21

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  WILSON, James ,  CELLINI, Ronald, A. ,  SOBOL, James, M.

IPC: H03M03/02

CPC classification number: H03M3/372 ,  H03M3/50

Abstract: A method and apparatus for analog-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional digital filtering techniques. In one embodiment, a sigma-delta ADC receives an analog input signal and converts the analog input signal to digital samples at an oversampling rate. A decimator, coupled to the sigma-delta ADC, receives the digital samples and decimates the digital samples to produce the digital samples at a preselected output sample rate, less than the oversampling rate. An ADC sample rate control circuit, coupled to the ADC, receives a frequency select signal representing the preselected output sample rate, and produces a noise-shaped clock signal for controlling operation of the ADC at the oversampling rate. The control circuit includes a sigma-delta modulator for sigma-delta modulating the frequency select signal. A randomizer/suppressor circuit, under control of the output of the sigma-delta modulator, receives an input clock signal and adjusts the frequency of the clock signal to produce a noise-shaped clock signal for controlling the oversampling rate of the ADC.

Abstract translation: 提供了一种使用数字样本之间的时间间隔的Σ-Δ调制进行模数转换的方法和装置。 该方法和装置包括时基的Σ-Δ调制，使得由非均匀采样产生的误差是频率形状的高频区域，其中它们被传统的数字滤波技术所减少。 在一个实施例中，Σ-ΔADC接收模拟输入信号，并以过采样率将模拟输入信号转换成数字采样。 耦合到Σ-ΔADC的抽取器接收数字采样并抽取数字采样，以预先选择的输出采样率产生数字样本，小于过采样率。 耦合到ADC的ADC采样率控制电路接收表示预选输出采样率的频率选择信号，并产生用于以过采样速率控制ADC的操作的噪声形状的时钟信号。 控制电路包括用于Σ-Δ调制频率选择信号的Σ-Δ调制器。 在Σ-Δ调制器的输出控制下的随机化器/抑制器电路接收输入时钟信号并调节时钟信号的频率以产生用于控制ADC的过采样率的噪声形时钟信号。

公开(公告)号：WO1996016471A1

公开(公告)日：1996-05-30

申请号：PCT/US1995015253

申请日：1995-11-22

Applicant: ANALOG DEVICES, INC. ,  GILBERT, Barrie

Inventor： ANALOG DEVICES, INC.

IPC: H03B05/02

CPC classification number: H03K3/0231 ,  H03B5/20 ,  H03H11/1291 ,  H03L5/00

Abstract: An oscillator (10) including two gm/C stages (12, 14) each including a differential pair of transistors (Q1, Q2; Q3, Q4), a capacitor (C3, C4), and a tunable current source (16, 26). The gm/C stages include a pair of input terminals (18, 20; 28, 30), a pair of output terminals (22, 24; 32, 34), and a pair of common-mode terminals (23, 25; 33, 35). The two gm/C stages are interconnected in a feedback loop to form a quadrature oscillator. A common-mode biasing circuit (36, 40) is coupled between a supply voltage and each pair of common-mode terminals for biasing the respective gm/C stage. An optional start-up circuit (38, 42) can be coupled to each gm/C stage to ensure start-up of the associated gm/C stage.

Abstract translation: 包括两个gm / C级（12,14）的振荡器（10），每个级分包括差分对晶体管（Q1，Q2; Q3，Q4），电容器（C3，C4）和可调谐电流源 ）。 gm / C级包括一对输入端子（18,20; 28,30），一对输出端子（22,24; 32,34）和一对共模端子（23,25; 33 ，35）。 两个gm / C级在反馈回路中互连形成正交振荡器。 共模偏置电路（36,40）耦合在电源电压和每对共模端子之间，用于偏置各个gm / C级。 可选的启动电路（38,42）可以耦合到每个gm / C级，以确保关联的gm / C级的启动。