公开(公告)号：EP0149322A3

公开(公告)日：1987-07-29

申请号：EP84308318

申请日：1984-11-30

Applicant: Hewlett-Packard Company

Inventor： Miller, Brian Mark

IPC: H03B05/02 ,  H03C03/22

CPC classification number: H03B5/02 ,  H03B2200/004 ,  H03B2200/0088 ,  H03C3/22 ,  H03J2200/36

Abstract: The deliberate use of multiple, seemingly redundant, varactor diodes (20) to reduce noise in applications where a single varactor diode would otherwise be adequate is described.

公开(公告)号：EP0110595A3

公开(公告)日：1986-10-15

申请号：EP83306805

申请日：1983-11-08

Applicant: HAZELTINE CORPORATION

Inventor： Muth, Robert N.

IPC: H03B05/12 ,  H03B05/02

CPC classification number: H03B5/1231 ,  H03B5/1203 ,  H03B5/1243 ,  H03B2200/004 ,  H03B2201/0208

Abstract: An oscillator (20) having sufficient accuracy and precision for use in aircraft microwave-landing systems is constructed without the use of an external inductor. A resonant tank circuit comprising both capacitance and inductance is attained by the use of inductance found internally in the base-emitter (28, 30) junction of a transistor suitably biased for operation at the frequencies of a microwave landing system. A transistor having greater-than-unity gain in the oscillation-frequency range is selected for which the angle of the reflection coefficient (S 11 ) is positive in theoscillation-frequency range.

公开(公告)号：EP0185908A3

公开(公告)日：1987-12-02

申请号：EP85114445

申请日：1985-11-13

Applicant: GTE LABORATORIES INCORPORATED

Inventor： Regan, Robert J. ,  Butler, Scott J. ,  Ben-Aharon, Zvi

IPC: H03F03/193 ,  H03B05/02 ,  H03F01/02

CPC classification number: H03F3/1935 ,  H03B5/1203 ,  H03B5/1228 ,  H03B5/1231 ,  H03B2200/0008 ,  H03B2200/0062 ,  H03F1/0283

Abstract: @ Energy source of a low power high frequency oscillator section (10) driving a high power high gain amplifier section (12). The amplifier section (12) includes one or more SIT's (Q2). The dc operating potential is applied. to the drain electrode of one of the SIT's (Q2) and is supplied to the other through a dc path from the source electrode of the one SITto the drain electrode of the other. Operating potential from the dc biasing network between the source and gate electrode of an SIT (Q2) in the amplifier section is conducted through a dc path to a transistor (Q1) in the oscillator section (10) to provide operating power for the oscillator section (10). The oscillator output is connected through a high freouency coupling dc blocking path to the amplifier input to provide a drive signal to be amplified and extracted at the amplifier output (14).

公开(公告)号：WO1996016471A1

公开(公告)日：1996-05-30

申请号：PCT/US1995015253

申请日：1995-11-22

Applicant: ANALOG DEVICES, INC. ,  GILBERT, Barrie

Inventor： ANALOG DEVICES, INC.

IPC: H03B05/02

CPC classification number: H03K3/0231 ,  H03B5/20 ,  H03H11/1291 ,  H03L5/00

Abstract: An oscillator (10) including two gm/C stages (12, 14) each including a differential pair of transistors (Q1, Q2; Q3, Q4), a capacitor (C3, C4), and a tunable current source (16, 26). The gm/C stages include a pair of input terminals (18, 20; 28, 30), a pair of output terminals (22, 24; 32, 34), and a pair of common-mode terminals (23, 25; 33, 35). The two gm/C stages are interconnected in a feedback loop to form a quadrature oscillator. A common-mode biasing circuit (36, 40) is coupled between a supply voltage and each pair of common-mode terminals for biasing the respective gm/C stage. An optional start-up circuit (38, 42) can be coupled to each gm/C stage to ensure start-up of the associated gm/C stage.

Abstract translation: 包括两个gm / C级（12,14）的振荡器（10），每个级分包括差分对晶体管（Q1，Q2; Q3，Q4），电容器（C3，C4）和可调谐电流源 ）。 gm / C级包括一对输入端子（18,20; 28,30），一对输出端子（22,24; 32,34）和一对共模端子（23,25; 33 ，35）。 两个gm / C级在反馈回路中互连形成正交振荡器。 共模偏置电路（36,40）耦合在电源电压和每对共模端子之间，用于偏置各个gm / C级。 可选的启动电路（38,42）可以耦合到每个gm / C级，以确保关联的gm / C级的启动。

公开(公告)号：WO1985000941A1

公开(公告)日：1985-02-28

申请号：PCT/US1984001241

申请日：1984-08-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CAMPBELL, David, L.

IPC: H03B05/02

CPC classification number: H03K3/0315 ,  H03K3/70 ,  H03K9/06 ,  H03K2005/00097 ,  H03K2005/00176 ,  H03L7/07 ,  H03L7/0995 ,  Y10S331/03

Abstract: As shown in (Fig. 2A), the fall time of an ECL gate (20) is precisely controlled using a fixed capacitor (46) which is connected between the positive supply voltage and the ECL gate output terminal (44), and a variable current source (48, 50, 52) connected between ground (GRND 3) and the ECL gate output terminal (44). A time-delay circuit is obtained by controlling the variable current source with an error voltage (VR2) of a phase-locked loop such that the time-delay precisely tracks the frequency of the reference signal for the phase-locked loop. A signal detector circuit is obtained by combining time-delay circuits. A voltage-controlled oscillator is assembled by connecting 3 ECL gates (12, 14, 16), as shown Fig. 1, with controlled fall times in a ring oscillator configuration. Addition of a noninverting input (19) to one ECL gate (16) makes the voltage-controlled oscillator interruptible. Combining a voltage-controlled oscillator of the type described with a phase detector fed by a reference signal provides a phase-locked loop with the control voltage thereof providing a frequency-to-voltage conversion function. A system for providing a receiver clock reference signal from a received signal is provided, as shown in Figs. 5A and 5B, by phase-locking the output signal of a first phase-locked loop (130) to a system reference signal (TCK) to generate a first-loop control voltage (X4). A second phase-locked loop is phase-locked to the received signal (MNCK) with a second-loop control voltage (VR4). In addition, the second phase-locked loop (142) is also frequency-locked to the system reference signal (TCK) by the first-loop control voltage (X4). This system is particularly useful for recovering a receiver clock reference from a Manchester-encoded signal.

Abstract translation: 如图2A所示，使用连接在正电源电压和ECL门输出端子（44）之间的固定电容器（46）精确地控制ECL门（20）的下降时间，并且可变 连接在地（GRND 3）和ECL门输出端（44）之间的电流源（48,50,52）。 通过以锁相环的误差电压（VR2）控制可变电流源，使得时间延迟精确地跟踪用于锁相环的参考信号的频率来获得延时电路。 通过组合时间延迟电路获得信号检测器电路。 通过连接3个ECL门（12,14,16）来组装压控振荡器，如图1所示。 1，具有环形振荡器配置中受控的下降时间。 将一个非反相输入（19）添加到一个ECL门（16）使得压控振荡器可中断。 将所描述类型的压控振荡器与由参考信号馈送的相位检测器相结合，提供锁相环，其控制电压提供频率 - 电压转换功能。 提供了一种从接收信号提供接收机时钟参考信号的系统，如图1和2所示。 参考图5A和5B，通过将第一锁相环（130）的输出信号相互锁定到系统参考信号（TCK）以产生第一回路控制电压（X4）。 第二个锁相环与具有第二回路控制电压（VR4）的接收信号（MNCK）锁相。 此外，第二锁相环（142）也通过第一回路控制电压（X4）而被频率锁定到系统参考信号（TCK）。 该系统对于从曼彻斯特编码的信号恢复接收机时钟参考特别有用。