公开(公告)号：US20230154897A1

公开(公告)日：2023-05-18

申请号：US18156287

申请日：2023-01-18

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L25/065 ,  H01L23/24 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/24 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/16 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/24155 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

公开(公告)号：US11646302B2

公开(公告)日：2023-05-09

申请号：US17013279

申请日：2020-09-04

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jie-Hua Zhao ,  Jun Zhai ,  Po-Hao Chang ,  Hsien-Che Lin ,  Ying-Chieh Ke ,  Kunzhong Hu

IPC: H01L25/18 ,  H01L23/24

CPC classification number: H01L25/18 ,  H01L23/24

Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

公开(公告)号：US20230017445A1

公开(公告)日：2023-01-19

申请号：US17815893

申请日：2022-07-28

Applicant: Apple Inc.

Inventor： Kunzhong Hu ,  Chonghua Zhong ,  Jiongxin Lu ,  Jun Zhai

IPC: H01L23/14 ,  H01L25/065 ,  H01L23/28 ,  H01L23/00 ,  H01L21/56 ,  H01L23/488

Abstract: Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. The interposer may be stacked on the package substrate and joined with a conductive film, and may be formed on the package substrate during a reconstitution sequence.

公开(公告)号：US11532563B2

公开(公告)日：2022-12-20

申请号：US17026708

申请日：2020-09-21

Applicant: Apple Inc.

Inventor： Karthik Shanmugam ,  Jun Zhai ,  Rajasekaran Swaminathan

IPC: H01L23/538 ,  H01L23/31 ,  H05K1/18 ,  H01L21/56 ,  H01L25/16

Abstract: Packages and packaging techniques are described in which a patterned carrier substrate can be used to create a reconstituted fanout substrate with a topography that can accommodate components of different thicknesses. In an embodiment, a wiring layer is formed directly on a multiple level topography of a molding compound layer including embedded components.

公开(公告)号：US20220199517A1

公开(公告)日：2022-06-23

申请号：US17133096

申请日：2020-12-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kunzhong Hu ,  Raymundo M. Camenforte

IPC: H01L23/528 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.

公开(公告)号：US20220157782A1

公开(公告)日：2022-05-19

申请号：US17457350

申请日：2021-12-02

Applicant: Apple Inc.

Inventor： Jun Zhai

IPC: H01L25/065

Abstract: Reconstructed 3DIC structures and methods of manufacture are described. In an embodiment, one or more dies in each package level of a 3DIC are both functional chips and/or stitching devices for two or more dies in an adjacent package level. Thus, each die can function as a communication bridge between two other dies/chiplets in addition to performing a separate chip core function.

公开(公告)号：US11309246B2

公开(公告)日：2022-04-19

申请号：US16783132

申请日：2020-02-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18 ,  H01L23/00

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US20210366861A1

公开(公告)日：2021-11-25

申请号：US16879596

申请日：2020-05-20

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/00

Abstract: Electronic packages and modules are described. In an embodiment, a hybrid thermal interface material including materials with different thermal conductivities is used to attach a lid to a device. In an embodiment, a low temperature solder material is included as part of an adhesion layer for attachment with a stiffener structure.

公开(公告)号：US11069665B2

公开(公告)日：2021-07-20

申请号：US16205679

申请日：2018-11-30

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Chonghua Zhong ,  Jun Zhai ,  Long Huang ,  Mengzhi Pang ,  Rohan U. Mandrekar

IPC: H01L25/16 ,  G01R31/64 ,  H01L23/525 ,  H01L21/66 ,  H01L49/02

Abstract: Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.

公开(公告)号：US20210202332A1

公开(公告)日：2021-07-01

申请号：US16729094

申请日：2019-12-27

Applicant: Apple Inc.

Inventor： Kunzhong Hu ,  Chonghua Zhong ,  Jiongxin Lu ,  Jun Zhai

IPC: H01L23/14 ,  H01L25/065 ,  H01L23/28 ,  H01L23/488 ,  H01L23/00 ,  H01L21/56

Abstract: Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. In an embodiment, the interposer is stacked on the package substrate and joined with a conductive film. In an embodiment the interposer is formed on the package substrate during a reconstitution sequence.