公开(公告)号：US20250158619A1

公开(公告)日：2025-05-15

申请号：US19022212

申请日：2025-01-15

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Bahattin Kilic ,  Jie-Hua Zhao ,  Kunzhong Hu ,  Suk-Kyu Ryu

IPC: H03K19/1776 ,  G06F15/78 ,  H01L23/31 ,  H05K1/02

Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

公开(公告)号：US20250158519A1

公开(公告)日：2025-05-15

申请号：US19021045

申请日：2025-01-14

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Jun Zhai ,  Ralf M. Schmitt ,  Vidhya Ramachandran ,  Wenjie Mao

IPC: H02M3/07 ,  G05F3/10 ,  H01L23/00 ,  H01L23/522 ,  H10D1/00

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

公开(公告)号：US11862481B2

公开(公告)日：2024-01-02

申请号：US17460806

申请日：2021-08-30

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Chi Nung Ni ,  Long Huang ,  SivaChandra Jangam

IPC: H01L21/56 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L21/56 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/32059 ,  H01L2224/32137 ,  H01L2924/183

Abstract: Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.

公开(公告)号：US11728266B2

公开(公告)日：2023-08-15

申请号：US17133096

申请日：2020-12-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kunzhong Hu ,  Raymundo M. Camenforte

IPC: H01L23/528 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/585 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/32145

Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.

公开(公告)号：US20230098000A1

公开(公告)日：2023-03-30

申请号：US17485022

申请日：2021-09-24

Applicant: Apple Inc.

Inventor： Chi Nung Ni ,  Sanjay Dabral

IPC: H02M1/15 ,  H02M3/158 ,  G06F1/3206

Abstract: Increases in current drawn from power supply nodes in a computer system can result in unwanted drops in the voltages of the power supply nodes until power supply circuits can compensate for the increased load. To lessen the effects of increases in load currents, a decoupling circuit that includes a diode may be coupled to the power supply node. During a charge mode, a control circuit applies a current to the diode to store charge in the diode. During a boost mode, the control circuit can couple the diode to the power supply node. When the voltage level of the power supply node begins to drop, the diode can source a current to the power supply node using the previously stored charge. The diode may be directly coupled to the power supply node or be part of a switch-based system that employs multiple diodes to increase the discharge voltage.

公开(公告)号：US11309895B2

公开(公告)日：2022-04-19

申请号：US16911902

申请日：2020-06-25

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Bahattin Kilic ,  Jie-Hua Zhao ,  Kunzhong Hu ,  Suk-Kyu Ryu

IPC: H03K19/1776 ,  G06F15/78 ,  H01L23/31 ,  H05K1/02

Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

公开(公告)号：US20220013504A1

公开(公告)日：2022-01-13

申请号：US17484188

申请日：2021-09-24

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US11101732B2

公开(公告)日：2021-08-24

申请号：US16943139

申请日：2020-07-30

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Jun Zhai ,  Ralf M. Schmitt ,  Vidhya Ramachandran ,  Wenjie Mao

IPC: H02M3/07 ,  G05F3/10 ,  H01L29/66 ,  H01L23/00 ,  H01L23/522

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

公开(公告)号：US20210217702A1

公开(公告)日：2021-07-15

申请号：US17216278

申请日：2021-03-29

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai

IPC: H01L23/538 ,  H01L23/488 ,  H01L23/00 ,  H01L25/18 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/498

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US20180294230A1

公开(公告)日：2018-10-11

申请号：US15801163

申请日：2017-11-01

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zun Zhai

IPC: H01L23/538 ,  H01L23/488 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L22/32 ,  H01L22/34 ,  H01L23/488 ,  H01L23/522 ,  H01L23/5283 ,  H01L23/58 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.