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公开(公告)号：JPS6046638A
公开(公告)日：1985-03-13
申请号：JP15470483
申请日：1983-08-24
Applicant: FUJITSU LTD
Inventor： MITA TERUYOSHI
Abstract: PURPOSE:To improve the efficiency of communication by inputting carrier transmission completion information to a time slot coupling between a circuit corresponding part connecting a circuit including a MODEM and a circuit corresponding part directly connected to a terminal. CONSTITUTION:A frame consisting of a frame head and plural time slots is made to flow into a corresponding part LSa on the MODEM3 side and a corresponding part LSb on the terminal 1-2 side and each time slot corresponds to a node. Each time slot includes carrier information RSCD and carrier transmission completion information CS together with data. At the start of communication, the terminal outputs a carrier sending request signal to the corresponding part LSb, a communication system detects the signal and transmits the detected signal to the corresponding part LSa as the carrier information RSCD to turn on the RS terminal of the MODEM. Consequently, the corresponding part LSa is immediately transmitted to the corresponding part LSb as the carrier transmission completing information CS.
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公开(公告)号：JPS59181848A
公开(公告)日：1984-10-16
申请号：JP5583283
申请日：1983-03-31
Applicant: Fujitsu Ltd
Inventor： MITA TERUYOSHI
CPC classification number: H04L41/06
Abstract: PURPOSE:To detect strictly the duplication of device number by discriminating it as the duplication of device number if a response signal to a check command is received from a higher rank station while a station is in the middle of transmitting the identical response signal to a lower rank station. CONSTITUTION:A signal is received by a signal converter 1 through a line l1 and the transmission signal is transmitted to a line l2 by a signal converter 7. Since a control terminal Rs of a control section 2 is logical ''0'' normally, a receiving signal is bypassed to an AND circuit 3 and an OR circuit 5 and transmitted to the line l2. When the check command is received, an MPU (microprocessor) 8 checks an interruption device number. If the number is coincident, the terminal Rs is brought to logical ''0'' and a response signal is transmitted from a transmission output terminal Tx. If other response signal is received during the response, it is discriminated as the duplication of the device number.
Abstract translation: 目的：如果从站点处于发送相同响应信号的中间到较低级站的中间，如果从更高级站接收到对检查命令的响应信号，则通过将其识别为设备号码的重复来严格检测设备号码的复制。 等级站。 构成：信号由信号转换器1通过线路l1接收，发送信号由信号转换器7发送到线路12.由于控制部分2的控制端子Rs正常为逻辑“0” 接收信号被旁路到AND电路3和OR电路5并传输到线路12。 当接收到检查命令时，MPU（微处理器）8检查中断设备号码。 如果数字一致，则将终端Rs变为逻辑“0”，并从发送输出端子Tx发送响应信号。 如果响应期间接收到其他响应信号，则将其识别为设备编号的重复。
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公开(公告)号：JPS59174049A
公开(公告)日：1984-10-02
申请号：JP4795183
申请日：1983-03-24
Applicant: Fujitsu Ltd
Inventor： NAKAHARA YASUHIRO , MITA TERUYOSHI , KITANO YOSHIHIRO , NAKAMURA OSAMU , NEGISHI HITOSHI
CPC classification number: H04L43/50
Abstract: PURPOSE:To prevent an evil effect to be exerted on the communication of other circuit corresponding parts and to detect instantaneously a faulty point, by using the blank time of communication to diagnose an address comparator at the circuit corresponding part within a station node. CONSTITUTION:A time slot address which is set within a circuit corresponding part from a program control part 6 by means of a frame synchronizing pattern is informed to an address buffer 13 within a circuit control part 8. At the same time, a diagnosis indication 25 is informed to a selection part 14. The part 8 delivers a signal 26 showing the busy state of the part 6 from the part 14. A corresponding part 9 collates the time slots fed from the buffer 13 through a comparator 18 and delivers a time slot reception signal 23 when the coincidence of collation is obtained to inform the coincidence to a transmitting part 20, a receiving part 21 and an address check buffer 24 of the control part 8 respectively. Then the part 8 informs the address check result to the control part 6.
Abstract translation: 目的：为了防止对其他电路对应部件的通信产生不利影响，并通过使用通信的空白时间诊断站节点内的电路对应部分的地址比较器，来对其进行瞬时检测。 构成：通过帧同步模式将来自程序控制部分6的电路对应部分内设置的时隙地址通知给电路控制部分8内的地址缓冲器13.同时，诊断指示25 通知给选择部分14.部分8从部分14传送表示部分6的忙状态的信号26.对应部分9将从缓冲器13馈送的时隙通过比较器18进行比较，并传送时隙 接收信号23，当获得对准的一致时，分别通知控制部分8的发送部分20，接收部分21和地址检查缓冲器24。 然后，部件8通知控制部分6的地址检查结果。
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公开(公告)号：JPS5935451B2
公开(公告)日：1984-08-29
申请号：JP15511777
申请日：1977-12-23
Applicant: Fujitsu Ltd
Inventor： SAWADA TAKETOYO , HANADA AKIO , MITA TERUYOSHI , HOSHI FUMIO , SATO MASAO
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公开(公告)号：JPS5957544A
公开(公告)日：1984-04-03
申请号：JP15048182
申请日：1982-08-30
Applicant: Fujitsu Ltd
Inventor： TAKEYAMA AKIRA , TAZAKI TAKASHI , NOJIMA SATOSHI , ARITAKA TOKUHIRO , MITA TERUYOSHI
IPC: H04L12/437
CPC classification number: H04L12/437
Abstract: PURPOSE:To form the loopback in a short time at the generation of a failure, by providing some discriminating functions to each node. CONSTITUTION:An input signal of the systems 0 and 1 is received at a receiving section RV of a control circuit CT in each node and the input signal is checked at a level regenerating circuit LV and a clock synchronism circuit CLS. As a result, a loopback control circuit LBC determines a failure state of the pre-stage and command information of the loopback based on the input from the LV and the CSL of the systems 0 and 1 and feeds an output to a transmission switching circuit TLC and a failure information systhesizing circuit EDC. The TLC executes arithmetic logically the input signal from the systems 0,1 and the signal of the loopback to form a prescribed loopback. Further, when a failure detecting signal of the system 0 or 1 is produced to the output of the LBC, it is informed to the next stage with the EDC. Thus, the period from the generation of failure to the formation of loopback is shortened extremely.
Abstract translation: 目的：通过为每个节点提供一些区分功能，在短时间内形成环路故障。 构成：在每个节点的控制电路CT的接收部分RV处接收系统0和1的输入信号，并且在电平再生电路LV和时钟同步电路CLS检查输入信号。 结果，环回控制电路LBC基于来自系统0和1的LV和CSL的输入确定前级的故障状态和命令信息，并将输出馈送到传输切换电路TLC 和故障信息检测电路EDC。 TLC在逻辑上执行来自系统0,1的输入信号和环回的信号以形成规定的环回。 此外，当向LBC的输出产生系统0或1的故障检测信号时，通过EDC通知下一级。 因此，从故障发生到环回形成的时期被极大地缩短。
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Patent Agency Ranking
公开(公告)号：JPS5944147A
公开(公告)日：1984-03-12
申请号：JP15492682
申请日：1982-09-06
Applicant: Fujitsu Ltd
Inventor： MITA TERUYOSHI , NAKAHARA YASUHIRO
CPC classification number: H04L43/50
Abstract: PURPOSE:To diagnose the part corresponding to a circuit, by transmitting a test pattern to each part corresponding to the circuit from a, monitor station and comparing a folded pattern from said part with the transmitted pattern, in a loop transmitting system for fixedly assigned TDM. CONSTITUTION:A signal from a loop 1 is transmitted to a loop 2 through an S/P converter 4-2, buffer memory 4-1 and a P/S converter 4-10. The timing data for diagosing the part corresponding to a circuit is stored in a register 4-6. When the specified time arrives, a signal is outputted from a comparator 1 and a test pattern stored in an FIFO (first in first out) through an AND gate 4-7 is transmitted to the loop 2 through the P/S converter 4-10. A folded pattern signal from the circuit corresponding part is stored in an FIFO1 and compared with the transmitted pattern to diagnose the part corresponding to the circuit.
Abstract translation: 目的：为了诊断对应于电路的部分，通过将测试模式发送到与监视站对应的电路的每个部分，并将来自所述部分的折叠模式与发送模式进行比较，在用于固定分配TDM的环路发送系统 。 构成：来自环路1的信号通过S / P转换器4-2，缓冲存储器4-1和P / S转换器4-10发送到环路2。 用于诊断对应于电路的部分的定时数据被存储在寄存器4-6中。 当指定时间到达时，从比较器1输出信号，并且通过与门4-7存储在FIFO（先进先出）中的测试图案通过P / S转换器4-10发送到环路2 。 来自电路对应部分的折叠图案信号存储在FIFO1中，并与发送模式进行比较，以诊断与电路对应的部分。
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公开(公告)号：JPS58201437A
公开(公告)日：1983-11-24
申请号：JP8438282
申请日：1982-05-19
Applicant: Fujitsu Ltd
Inventor： INOUE YUKINORI , MITA TERUYOSHI , KITANO YOSHIHIRO
IPC: H04L1/22 , H04B10/032 , H04B10/035 , H04B10/07 , H04B10/079 , H04B10/275 , H04L1/14 , H04L12/42 , H04L12/437
CPC classification number: H04L1/14
Abstract: PURPOSE:To detect specifically, a section of a failure of a spare transmission line by diagnosing a transmission line between adjacent station nodes in each of many station nodes connected in a loop. CONSTITUTION:The nodes 3-1, 3-2... gives data from an existing transmission line 1 to a preceding node via a photoelectric converting circuit 6, a delay circuit 11, an electroopic converting circuit 9 and a spare transmission line 2. On the other hand, the data transmitted from a control logic 13 to a succeeding node via the existing transmission line 1 is inputted also to a comparison circuit 31 via a delay circuit 30 at the same time. The comparison circuit 31 monitors a failure in a transmission line between succeeding nodes, by comparing the data returned via the existing line 1, the preceding node, and the spare line 2, with the transmission data.
Abstract translation: 目的：通过诊断在循环中连接的许多站点节点之间的相邻站节点之间的传输线来检测备用传输线路故障的一部分。 结构：节点3-1,3-2 ...经由光电转换电路6，延迟电路11，电光转换电路9和备用传输线2将现有传输线1至前一节点的数据提供给前一节点。 另一方面，经由现有传输线1从控制逻辑13发送到后续节点的数据也经由延迟电路30同时输入到比较电路31。 比较电路31通过将经由现有线路1，前一节点和备用线路2返回的数据与发送数据进行比较来监视后续节点之间的传输线路中的故障。
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公开(公告)号：JPS58172044A
公开(公告)日：1983-10-08
申请号：JP5445582
申请日：1982-04-01
Applicant: FUJITSU LTD
Inventor： KITANO YOSHIHIRO , MITA TERUYOSHI
IPC: H04L1/00
Abstract: PURPOSE:To specify an error section at a highway monitor node in a data highway system, by allowing each station node to add check data to a check byte when sending out a frame. CONSTITUTION:Every time a frame arrives from a transmission line, a check is performed by using a frame check byte FCK. If an error is detected, error information is written. Then, the next frame is received and when no data is written at the node response part NRES of a frame header FHD, the node address NAD of a node detecting the error is written and the resulting frame is sent out to the transmission line. Further, the frame check byte FCK is sent out to the transmission line together with added check data. At the highway monitor node, the error section is specified by error information and the node address.
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公开(公告)号：JPS58114547A
公开(公告)日：1983-07-07
申请号：JP21400281
申请日：1981-12-26
Applicant: FUJITSU LTD
Inventor： KITANO YOSHIHIRO , MITA TERUYOSHI
IPC: H04L12/437
Abstract: PURPOSE:To attain the loop reconstitution of a switching loop from present use into spare, by installing plrual monitors on a loop, and monitoring the status of the monitor of the present use system by the monitor of the spare system. CONSTITUTION:If a failure occurs in a present use monitor 51, and arrives in a spare monitor 52, under the sate that bits of supervisor status are not controlled the monitor 52 releases the spare mode of the device itself and transmits the switching command of the reception line to exchanges 53-55 by using a transmission line 57 of the spare system. To the monitor 51, one bit of the supervisor status is used as the through-mode. After a prescribed time, when communication is executed by using the line 57, the monitor 52 plays the major role and trasmits a frame. In this case, the supervisor status is neglected.
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公开(公告)号：JPS57204663A
公开(公告)日：1982-12-15
申请号：JP8918381
申请日：1981-06-10
Applicant: FUJITSU LTD
Inventor： MITA TERUYOSHI , SAKATA TAKAO
IPC: H04B14/04 , H04L27/14 , H04L27/156
Abstract: PURPOSE:To obtain a simple constituted and economical carrier wave detecting means, by decoding signals obtained by converting FSK modulated waves into PCM codes. CONSTITUTION:Information converted into 8-bit PCM codes is sent to a register 2 from a digital network 1. A NAND gate 3 is for detecting PCM codes above a specified level in the register 2, and its output is stored in a flip flop 4. The output of the flip flop 4 is inputted into an exclusive-OR cirit 5 and the output of the circuit 5 is used for controlling the operating condition of a counter 6. The circuit composed of the exclusive-OR circuit 5 and the counter 6 is for outputting a carrier wave detection signal CD ''1'' to the output of the counter 6 when PCM codes above a prescribed level are continued for more than a prescribed period. This means that the carrier wave detecting signal CD is turned to ''0'' only when PCM codes below a prescribed level are continued for a prescribed period.
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