公开(公告)号：JP2000076163A

公开(公告)日：2000-03-14

申请号：JP24928598

申请日：1998-09-03

Applicant: Hitachi Ltd ,  株式会社日立製作所

Inventor： OKURA TAKANORI ,  YAMADA TSUTOMU ,  KUROSAWA KENICHI

IPC: G06F15/177 ,  G06F13/00 ,  H04L12/413

CPC classification number: H04L12/40013 ,  H04L47/50 ,  H04L47/564

Abstract: PROBLEM TO BE SOLVED: To provide a communication system capable of increasing processing performance regardless of the processing performance of a CPU. SOLUTION: A communication node is constituted of a communication controller 8 for transmitting information to be transmitted to a transmission line 9 by a transmission instruction and storing the information received from the transmission line 9 in a storage device 2 and a data processor for computing transmission time that the local communication node performs transmission, based on the received information and the information set to the local communication node beforehand by the detection of the write of the information received by the communication controller 8, counting the computed transmission time from the point of detecting the end of the write by the communication controller 8 and informing the communication controller 8 of an instruction for transmitting the information from the local communication node.

Abstract translation: 要解决的问题：提供能够提高处理性能的通信系统，而不管CPU的处理性能如何。 解决方案：通信节点由通信控制器8构成，通信控制器8用于通过发送指令发送要发送到传输线路9的信息，并将从传输线路9接收的信息存储在存储设备2中;以及数据处理器，用于计算传输时间 本地通信节点通过检测由通信控制器8接收到的信息的写入，基于接收到的信息和设置给本地通信节点的信息来执行传输，从计算出的传输时间 通过通信控制器8的写入结束，并向通信控制器8通知用于从本地通信节点发送信息的指令。

公开(公告)号：JPH10293697A

公开(公告)日：1998-11-04

申请号：JP10157897

申请日：1997-04-18

Applicant: HITACHI LTD

Inventor： HIUGA KAZUHIRO ,  MIYAZAKI YOSHIHIRO ,  TAKATANI SOICHI ,  KUROSAWA KENICHI ,  YAMAGUCHI SHINICHIRO

IPC: G06F13/14 ,  G06F1/04 ,  G06F11/18 ,  G06F11/20

Abstract: PROBLEM TO BE SOLVED: To exchange software without stopping a system by storing whether the system operates as a clock synchronous fault tolerant computer system or as an asynchronous multi-computer system. SOLUTION: A state storing means 150 stores two states that are the same operation state in which a system synchronizes with a clock and collectively operates the same program and an independent operation state in which plural computer systems independently operate. A separating/connecting means 160 divides a dual computer system into plural computer systems or unites plural computer systems into one computer system. Selecting means 200A and 200B select a clock from clock generator circuits 120 of their own processors. Also, a memory imprinting means 230 makes the memory in which both processors 120A and 120B are incorporated coincidental.

公开(公告)号：JPH10269134A

公开(公告)日：1998-10-09

申请号：JP7715697

申请日：1997-03-28

Applicant: HITACHI LTD

Inventor： ARITA YUTAKA ,  NAKAMIGAWA TETSUAKI ,  KUROSAWA KENICHI ,  OKAMOTO TADASHI ,  MIYAZAKI YOSHIHIRO

IPC: G06F12/02

Abstract: PROBLEM TO BE SOLVED: To improve the efficiency of data transfer between a controlling unit and a controlled device, by reading data rewritten by a memory controller so as to modify control contents, out of a memory and sending it. SOLUTION: State data showing the state of a controlled system and control data for controlling the controlled system are stored in a control memory 201 and a computer device 101 computes control data on the controlled system according to the stored state data. The state stored in the control memory 201 is read out by a memory controller 401, the computed data is written in the read state data, and the resulting data is stored in the control memory 201. Then the data which is thus rewritten by the memory controller 401 is read out of the control memory 201, outputted to a network 1200 by a data transfer device 301, and sent to the controlled device. Consequently, the data transfer between the control unit 1000 and controlled device can be made efficient.

公开(公告)号：JPH10232729A

公开(公告)日：1998-09-02

申请号：JP3464297

申请日：1997-02-19

Applicant: HITACHI LTD ,  HITACHI PROCESS COMPUTER ENG

Inventor： KAMINAGA YASUO ,  KUROSAWA KENICHI ,  YAMADA TSUTOMU ,  MASUI KOJI ,  OHASHI AKIHIRO ,  MATSUDA MASAHIRO

IPC: G06F1/18 ,  G06F3/00 ,  H05K7/14

Abstract: PROBLEM TO BE SOLVED: To prevent the generation of rapid current at the time of medium pin connection by limiting a 1st rush current through resistance and suppressing a 2nd rush current through inductance. SOLUTION: In the case of connecting time, a long pin 9 is first connected to VCC and a long pin 8 is connected to GND. A power supply current flows as a charging current through a rush resistor 6 to a load capacitor 1 and flows as a consumption current to a load resistor 2. When a medium pin 10 is connected to the VCC, the charging current to the load capacitor 1 and the consumption current to the load resistor 2 are allowed to flow gradually from the VCC through inductance 3 to the load almost from a remaining V0 (the voltage of load capacitor 1 and load resistor 2) to the VCC. At such a time, the current is branched to the parallel resistors of rush resistor 6 and parallel resistor 5 and the inductance 3. Since the exchange current from the power source VCC is prevented from getting rapid without enlarging the value of inductance 3, the load output voltage V0 is charged by 1st-order rush resistance 6 and branched to the rush resistance 6 and the parallel resistance 5 by 2nd-order rush and the current to the inductance is reduced.

公开(公告)号：JPH08234982A

公开(公告)日：1996-09-13

申请号：JP5129896

申请日：1996-03-08

Applicant: HITACHI LTD

Inventor： KUROSAWA KENICHI ,  TANAKA SHIGEYA ,  NAKATSUKA YASUHIRO ,  BANDO TADAAKI

IPC: G06F9/38

Abstract: PURPOSE: To secure the compatibility between the parallel processing and the sequential processing and to improve the processing capability of a parallel processor by giving a prescribed number of continuous instructions to plural arithmetic units from plural instruction registers respectively. CONSTITUTION: When the value of a processing state flag PE 116 of a processor status register 103 is set in an ON state, two instructions pointed by a program counter PC are read out and set at the 1st and 2nd instruction registers 104 and 105 through the buses 117 and 118 respectively. When an even number of PCs are provided, the instruction of address PC and the instruction of address (PC+1) are stored in the registers 104 and 105 respectively. Then a NOP instruction and the instruction of the address PC are set at the registers 104 and 105 respectively when an odd number of PCs are provided. When both registers 104 and 105 receive the branch instructions, the value of (PC+2) is set at a latch 102. Then a branch address is calculated and set at the PC when both registers 104 and 105 are branched.

公开(公告)号：JPH08124380A

公开(公告)日：1996-05-17

申请号：JP25549594

申请日：1994-10-20

Applicant: HITACHI LTD

Inventor： OGURA MAKOTO ,  KUROSAWA KENICHI ,  ISHIKAWA SUKETAKA ,  KURIHARA RYOICHI ,  OOISHI TSURATOKI

IPC: G06F12/14 ,  G06F21/02 ,  G11C11/401 ,  G11C11/407

Abstract: PURPOSE: To externally check whether the contents of a mode register are correctly set by providing a semiconductor memory with an output control logic circuit which outputs the data stored in the mode register to the bus. CONSTITUTION: A comparison circuit compares a key code 14 with the I/O bus 20 to output a logic value 1 to the wiring 25 only when these are equal. The output signal of the wiring 25 and the signal 21 outputted from a command decode unit 11 are inputted into a logic product circuit 12 so as to give a logic value 1 only when the wiring 25 and the signal 21 have both a logic value 1. Namely the output 26 of the circuit 12 transmits the signal 21 only when the bus 20 and the code 14 are equal. The output 26 of this circuit 12 becomes the setting signal 26 to set the value to a mode register 10 and hence the content of the address bus 52 is set to the register 10 and written when the signal 26 has a logic value 1. Through this, the content of the bus 52 is writable to the register 10 only when the bus 20 and the code 14 are completely equal and otherwise its writing is inhibited to protect the content of the register 10.

公开(公告)号：JPH06348590A

公开(公告)日：1994-12-22

申请号：JP13755293

申请日：1993-06-08

Applicant: HITACHI LTD ,  HITACHI COMPUTER ENG

Inventor： MIURA SHUICHI ,  KUROSAWA KENICHI ,  ISHIKAWA SUKETAKA ,  FUKUNAKA HIDETADA ,  NAGAI EIICHIRO

IPC: G06F12/06

Abstract: PURPOSE:To provide a main storage device of a small-sized computer such as a work station with nearly the same performance as the main storage device of a large-sized computer with a small physical quantity. CONSTITUTION:Plural storage parts (1-A0-1-A3, and 1-B0-1-B3) are constituted by providing with four groups of storage parts made of a couple of two storage parts (1-A0, 1-B0...), and the data lines of the couples of respective storage parts are made common and connected to a data part 4. A host computer 4 sends a request to access the main storage device to a control part 2. The control part 2 receives the access request and activates a storage part 1 through a control signal 2000-A or 2000-B. The control signal 2000-A activates the storage parts 1-A0-1-A3 and the control signal 2000-B activates the storage parts 1-B0-1-B3. Data read out of the storage parts 1-A0 and 1-B0 are inputted to the data part 3 through a common data line 3000-0 and the data part 3 switches the read data coming from the respective data lines 3000-0, 3000-1...3000-3 in order and transfers them to the host computer 4 through a data line 4000.

公开(公告)号：JPH063604B2

公开(公告)日：1994-01-12

申请号：JP3880585

申请日：1985-03-01

Applicant: HITACHI LTD

Inventor： KIRYAMA KAORU ,  ABE SHIGEO ,  KUROSAWA KENICHI ,  BANDO TADAAKI ,  NAKANISHI HIROAKI

IPC: G06F9/44 ,  G06F17/30 ,  G06F15/40 ,  G06F15/411

Abstract: PURPOSE:To perform hashing in a high speed to improve efficiency by reading out a hash value from a data storage area and allowing a function to act upon this hash value to obtain a value and indexing a table with an address obtained by adding the start address of the hash table to this obtained value. CONSTITUTION:A constant in a prologue program is expressed with constant information 1 consisting of a tag part 11 indicating the attribute and a data part 12 indicating the pointer address, and a hash value peculiar to the constant and an actual value 22 of the constant are stored in a data storage area 2 indicated by the pointer address of the data part 12. The hash value 21 is read out from the area 2 by the pointer address of the data part 12, and a prescribed function Fi is allowed to act upon the value 21 to obtain a value, and the start address of a hash table 3 is added to this obtained value to obtain an address on the table 3, and the table 3 is indexed by this address. Thus, hashing is performed in a high speed.

公开(公告)号：JPH0478554B2

公开(公告)日：1992-12-11

申请号：JP14654684

申请日：1984-07-13

Applicant: HITACHI LTD

Inventor： MIURA MASAKI ,  KUROSAWA KENICHI ,  HIRASAWA KOTARO ,  KUZUNUKI SOSHIRO ,  YONEDA KENJI ,  FUJII YASUO

IPC: B66B1/18

公开(公告)号：JPH0451474B2

公开(公告)日：1992-08-19

申请号：JP7817483

申请日：1983-05-06

Applicant: HITACHI LTD

Inventor： KUROSAWA KENICHI ,  MIURA MASAKI ,  HIRASAWA KOTARO ,  YONEDA KENJI

IPC: B66B1/20 ,  B66B1/18