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公开(公告)号：SG193162A1
公开(公告)日：2013-09-30
申请号：SG2013057922
申请日：2010-11-08
Applicant: IBM
Inventor： SCHWARZ ERIC MARK , YEH PHIL , COWLISHAW MICHAEL FREDERIC , MUELLER SILVIA MELITTA
Abstract: 23 DECIMAL FLOATING-POINT QUANTUM EXCEPTION DETECTION AbstractA system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The10 preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional15 processing. Fig. 1
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122.发明专利
公开(公告)号：CA2867088A1
公开(公告)日：2013-09-19
申请号：CA2867088
申请日：2012-11-15
Applicant: IBM
Inventor： BRADBURY JONATHAN DAVID , GSCHWIND MICHAEL KARL , SLEGEL TIMOTHY , SCHWARZ ERIC MARK , JACOBI CHRISTIAN
IPC: G06F9/34
Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.
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公开(公告)号：CA2800643A1
公开(公告)日：2011-12-01
申请号：CA2800643
申请日：2010-11-08
Applicant: IBM
Inventor： SCHWARZ ERIC MARK , YEH PHIL , COWLISHAW MICHAEL FREDERIC , MUELLER SILVIA MELITTA
Abstract: A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
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Patent Agency Ranking
公开(公告)号：DE68923262T2
公开(公告)日：1996-02-15
申请号：DE68923262
申请日：1989-11-24
Applicant: IBM
Inventor： VASSILIADIS STAMATIS , SCHWARZ ERIC MARK , SUNG BAIK MOON
Abstract: A multi-bit overlapped scanning multiplication system using overlapped partial products in a matrix, accepts and multiplies either sign-magnitude operands or signed binary operands without correction, conversion, or complementation of operands or results.
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公开(公告)号：DE68921663T2
公开(公告)日：1995-10-05
申请号：DE68921663
申请日：1989-04-04
Applicant: IBM
Inventor： VASSILIADIS STAMATIS , SCHWARZ ERIC MARK , FEAL BRICE JOHN , PUTRINO MICHAEL
Abstract: An apparatus for predicting parity of a result produced by selection of the most or least significant thirty-two bits produced by a thirty-four bit adder, the parity being predicted concurrently with and independently of the result. Parity for byte Si of the selected result is derived by circuitry implementing the relationship: Pi = yP(M,n-1) V P(n,M+7) V y min P(M+8, n+7) in which Pi is the parity bit for Si, y is the positive sense of a signal indicating selection, of the most significant thirty-two result bits, y min is the complement of y and indicates selection of the least significant thirty-two result bits, P(M,n-1) is parity over the two most significant result bits in the portion of the result covering result bits m through n+7, P(m+8, n+7) is parity of the two least significant bits of the result portion, P(n, m+7) is parity over the central bits of the portion, i is an integer and 0
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公开(公告)号：DE3853529D1
公开(公告)日：1995-05-11
申请号：DE3853529
申请日：1988-06-21
Applicant: IBM
Inventor： SCHWARZ ERIC MARK , VASSILIADIS STAMATIS
Abstract: A dynamic multiple instruction stream, multiple data, multiple pipeline (MIMD) apparatus simultaneously executes more than one instruction associated with a multiple number of instruction streams utilizing multiple data associated with the multiple number of instruction streams in a multiple number of pipeline processors. Since instructions associated with a multiple number of instruction streams are being executed simultaneously by a multiple number of pipeline processors, a tracking mechanism is needed for keeping track of the pipe in which each instruction is executing. As a result, a dynamic history table maintains a record of the pipeline processor number in which each incoming instruction is executing, and other characteristics of the instruction. When a particular instruction is received, it is decoded and its type is determined. Each pipeline processor handles a certain category of instructions; the particular instruction is transmitted to the pipeline processor having its corresponding category. However, before transmission, the pipeline processor is checked for completion of its oldest instruction by consulting the dynamic history table. If the table indicates that the oldest instruction in the pipeline processor should complete, execution of the oldest instruction in such processor completes, leaving room for insertion of the particular instruction therein for execution. When the particular instruction is transmitted to its associated pipeline processor, information including the pipe number is stored in the dynamic history table for future reference.
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公开(公告)号：DE68921663D1
公开(公告)日：1995-04-20
申请号：DE68921663
申请日：1989-04-04
Applicant: IBM
Inventor： VASSILIADIS STAMATIS , SCHWARZ ERIC MARK , FEAL BRICE JOHN , PUTRINO MICHAEL
Abstract: An apparatus for predicting parity of a result produced by selection of the most or least significant thirty-two bits produced by a thirty-four bit adder, the parity being predicted concurrently with and independently of the result. Parity for byte Si of the selected result is derived by circuitry implementing the relationship: Pi = yP(M,n-1) V P(n,M+7) V y min P(M+8, n+7) in which Pi is the parity bit for Si, y is the positive sense of a signal indicating selection, of the most significant thirty-two result bits, y min is the complement of y and indicates selection of the least significant thirty-two result bits, P(M,n-1) is parity over the two most significant result bits in the portion of the result covering result bits m through n+7, P(m+8, n+7) is parity of the two least significant bits of the result portion, P(n, m+7) is parity over the central bits of the portion, i is an integer and 0
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公开(公告)号：BR8804969A
公开(公告)日：1989-05-02
申请号：BR8804969
申请日：1988-09-27
Applicant: IBM
Inventor： SCHWARZ ERIC MARK , VASSILIADIS STAMATIS
Abstract: A dynamic multiple instruction stream, multiple data, multiple pipeline (MIMD) apparatus simultaneously executes more than one instruction associated with a multiple number of instruction streams utilizing multiple data associated with the multiple number of instruction streams in a multiple number of pipeline processors. Since instructions associated with a multiple number of instruction streams are being executed simultaneously by a multiple number of pipeline processors, a tracking mechanism is needed for keeping track of the pipe in which each instruction is executing. As a result, a dynamic history table maintains a record of the pipeline processor number in which each incoming instruction is executing, and other characteristics of the instruction. When a particular instruction is received, it is decoded and its type is determined. Each pipeline processor handles a certain category of instructions; the particular instruction is transmitted to the pipeline processor having its corresponding category. However, before transmission, the pipeline processor is checked for completion of its oldest instruction by consulting the dynamic history table. If the table indicates that the oldest instruction in the pipeline processor should complete, execution of the oldest instruction in such processor completes, leaving room for insertion of the particular instruction therein for execution. When the particular instruction is transmitted to its associated pipeline processor, information including the pipe number is stored in the dynamic history table for future reference.
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