公开(公告)号：US09543211B1

公开(公告)日：2017-01-10

申请号：US14864881

申请日：2015-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Yu-Cheng Tung ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Wei-Hao Huang ,  Chih-Sen Huang ,  Ching-Wen Hung

IPC: H01L21/70 ,  H01L21/8234 ,  H01L21/283 ,  H01L27/088

CPC classification number: H01L21/823437 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/088

Abstract: A manufacturing method of a semiconductor structure includes the following steps. Gate structures are formed on a semiconductor substrate. A source/drain contact is formed between two adjacent gate structures. The source/drain contact is recessed by a recessing process. A top surface of the source/drain contact is lower than a top surface of the gate structure after the recessing process. A stop layer is formed on the gate structures and the source/drain contact after the recessing process. A top surface of the stop layer on the source/drain contact is lower than the top surface of the gate structure. A semiconductor structure includes the semiconductor substrate, the gate structures, a gate contact structure, and the source/drain contact. The source/drain contact is disposed between two adjacent gate structures, and the top surface of the source/drain contact is lower than the top surface of the gate structure.

Abstract translation: 半导体结构的制造方法包括以下步骤。 栅极结构形成在半导体衬底上。 在两个相邻栅极结构之间形成源极/漏极接触。 源极/漏极接触器通过凹陷工艺凹陷。 源极/漏极接触件的顶表面在凹陷过程之后低于栅极结构的顶表面。 在凹陷过程之后，在栅极结构和源极/漏极触点上形成阻挡层。 源极/漏极接触点上的阻挡层的顶表面低于栅极结构的顶表面。 半导体结构包括半导体衬底，栅极结构，栅极接触结构和源极/漏极接触。 源极/漏极触点设置在两个相邻的栅极结构之间，源极/漏极接触的顶表面低于栅极结构的顶部表面。

公开(公告)号：US20160380077A1

公开(公告)日：2016-12-29

申请号：US15263349

申请日：2016-09-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/66 ,  H01L29/51 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/165 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/66628

Abstract: A method for manufacturing a semiconductor device having metal gates includes following steps. A substrate including a first transistor and a second transistor formed thereon is provided. The first transistor includes a first gate trench and the second transistor includes a second gate trench. A patterned first work function metal layer is formed in the first gate trench and followed by forming a second sacrificial masking layer respectively in the first gate trench and the second gate trench. An etching process is then performed to form a U-shaped first work function metal layer in the first gate trench. Subsequently, a two-step etching process including a strip step and a wet etching step is performed to remove the second sacrificial masking layer and portions of the U-shaped first work function metal layer to form a taper top on the U-shaped first work function metal layer in the first gate trench.

Abstract translation: 制造具有金属栅极的半导体器件的方法包括以下步骤。 提供了包括形成在其上的第一晶体管和第二晶体管的衬底。 第一晶体管包括第一栅极沟槽，第二晶体管包括第二栅极沟槽。 在第一栅极沟槽中形成图案化的第一功函数金属层，然后分别在第一栅极沟槽和第二栅极沟槽中形成第二牺牲掩模层。 然后进行蚀刻工艺以在第一栅极沟槽中形成U形的第一功函数金属层。 随后，执行包括条带步骤和湿蚀刻步骤的两步蚀刻工艺，以去除第二牺牲掩模层和U形第一功函数金属层的部分以在U形第一工件上形成锥形顶部 功能金属层在第一栅极沟槽中。

公开(公告)号：US20160322468A1

公开(公告)日：2016-11-03

申请号：US14723467

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Wei-Hao Huang

IPC: H01L29/423 ,  H01L29/51 ,  H01L23/535

CPC classification number: H01L29/42364 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/51 ,  H01L29/518 ,  H01L29/785

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around the gate structure; a first contact plug in the ILD layer; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and a spacer between the second contact plug and the second dielectric layer.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 基板上的栅极结构; 围绕栅极结构的层间电介质（ILD）; ILD层中的第一接触插塞; ILD层上的第二介电层; 第二接触插塞在第二电介质层中并电连接到第一接触插塞; 以及在第二接触插塞和第二电介质层之间的间隔物。

公开(公告)号：US20160163532A1

公开(公告)日：2016-06-09

申请号：US14562768

申请日：2014-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Chieh-Te Chen

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/0206 ,  H01L21/02186 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a hard mask on the gate structure and the ILD layer; forming a first patterned mask layer on the hard mask; using the first patterned mask layer to remove part of the hard mask for forming a patterned hard mask; and utilizing a gas to strip the first patterned mask layer while forming a protective layer on the patterned hard mask, wherein the gas is selected from the group consisting of N2 and O2.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上至少具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构和ILD层上形成硬掩模; 在硬掩模上形成第一图案化掩模层; 使用第一图案化掩模层去除用于形成图案化硬掩模的硬掩模的一部分; 并且利用气体剥离第一图案化掩模层，同时在图案化的硬掩模上形成保护层，其中气体选自N2和O2。

公开(公告)号：US09324620B2

公开(公告)日：2016-04-26

申请号：US14462574

申请日：2014-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823456 ,  H01L21/28088 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a second metal gate structure is disposed within the iso region. The first metal gate structure includes a first trench disposed within the dense region, and a first metal layer disposed within the first trench. The second metal gate structure includes a second trench disposed within the iso region, and a second metal layer disposed within the second trench. The height of the second metal layer is greater than the height of the first metal layer.

Abstract translation: 金属栅极结构包括具有致密区域和iso区域的基板。 第一金属栅极结构设置在致密区域内，第二金属栅极结构设置在iso区域内。 第一金属栅极结构包括设置在密集区域内的第一沟槽和设置在第一沟槽内的第一金属层。 第二金属栅极结构包括设置在iso区内的第二沟槽和设置在第二沟槽内的第二金属层。 第二金属层的高度大于第一金属层的高度。

公开(公告)号：US09263540B1

公开(公告)日：2016-02-16

申请号：US14852624

申请日：2015-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

Abstract translation: 金属栅极结构至少包括衬底，电介质层，第一和第二沟槽，第一金属层和第二金属层以及两个盖层。 特别地，介电层设置在基板上，并且第一和第二沟槽设置在电介质层中。 第一沟槽的宽度小于第二沟槽的宽度。 第一和第二金属层分别设置在第一沟槽和第二沟槽中，第一金属层的高度小于或等于第二金属层的高度。 盖层分别设置在第一金属层的顶表面和第二金属层的顶表面中。

公开(公告)号：US20160005658A1

公开(公告)日：2016-01-07

申请号：US14462574

申请日：2014-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L21/823456 ,  H01L21/28088 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a second metal gate structure is disposed within the iso region. The first metal gate structure includes a first trench disposed within the dense region, and a first metal layer disposed within the first trench. The second metal gate structure includes a second trench disposed within the iso region, and a second metal layer disposed within the second trench. The height of the second metal layer is greater than the height of the first metal layer.

Abstract translation: 金属栅极结构包括具有致密区域和iso区域的基板。 第一金属栅极结构设置在致密区域内，第二金属栅极结构设置在iso区域内。 第一金属栅极结构包括设置在致密区域内的第一沟槽和设置在第一沟槽内的第一金属层。 第二金属栅极结构包括设置在iso区内的第二沟槽和设置在第二沟槽内的第二金属层。 第二金属层的高度大于第一金属层的高度。

公开(公告)号：US09230864B1

公开(公告)日：2016-01-05

申请号：US14515534

申请日：2014-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Shi-Xiong Lin

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7831 ,  H01L29/7833

Abstract: A method of forming a semiconductor device having a metal gate includes the following steps. First of all, a first gate trench is formed in a dielectric layer. Next, a first work function layer is formed, covering the first gate trench. Then, a protection layer is formed in the first gate trench, also on the first work function layer. Then, a patterned sacrificial mask layer is formed in the first gate trench to expose a portion of the protection layer. After that, the exposed protection layer is removed, to form a U-shaped protection layer in the first gate trench. As following, a portion of the first work function layer under the exposed protection layer is removed, to form a U-shaped first work function layer in the first gate trench. Finally, the patterned sacrificial mask layer and the U-shaped protection layer are completely removed.

Abstract translation: 一种形成具有金属栅极的半导体器件的方法包括以下步骤。 首先，在电介质层中形成第一栅极沟槽。 接下来，形成覆盖第一栅沟槽的第一功函数层。 然后，也在第一功函数层上的第一栅极沟槽中形成保护层。 然后，在第一栅极沟槽中形成图案化的牺牲掩模层以暴露保护层的一部分。 之后，去除暴露的保护层，以在第一栅极沟槽中形成U形保护层。 如下，去除暴露的保护层下面的第一功函数层的一部分，以在第一栅极沟槽中形成U形的第一功函数层。 最后，图案化的牺牲掩模层和U形保护层被完全去除。

公开(公告)号：US09023708B2

公开(公告)日：2015-05-05

申请号：US13866456

申请日：2013-04-19

Applicant: United Microelectronics Corp.

Inventor： Li-Chiang Chen ,  Jiunn-Hsiung Liao ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai ,  Ching-Pin Hsu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/42372 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823828 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.

Abstract translation: 提供一种形成半导体器件的方法。 在基板上形成包括虚拟栅极的至少一个栅极结构。 形成接触蚀刻停止层和电介质层以覆盖栅极结构。 接触蚀刻停止层的一部分和电介质层的一部分被去除以暴露栅极结构的顶部。 执行干蚀刻处理以去除栅极结构的虚拟栅极的一部分。 对剩余的虚拟栅极的表面进行氢化处理。 执行湿蚀刻处理以去除剩余的虚拟栅极，从而形成栅极沟槽。

公开(公告)号：US20140349476A1

公开(公告)日：2014-11-27

申请号：US13902977

申请日：2013-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Yu-Tsung Lai ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485

Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.

Abstract translation: 本发明提供一种半导体器件的制造方法，至少包括以下步骤：首先，提供基板，其中在基板上形成第一介电层，在第一介电层中形成至少一个金属栅极， 至少一个源极漏极区域（S / D区域）设置在金属栅极的两侧，然后在第一介电层中形成至少一个第一沟槽，暴露S / D区域的部分。 用于形成第一沟槽的制造方法还包括通过第一光掩模执行第一光刻工艺并通过第二光掩模执行第二光刻工艺，并且在第一电介质层中形成至少一个第二沟槽，暴露金属栅极的部分 并且最后，在每个第一沟槽和每个第二沟槽中填充导电层。