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    DYNAMIC COLUMN BLOCK SELECTION
    122.
    发明公开
    DYNAMIC COLUMN BLOCK SELECTION 有权
    动态列块选择

    公开(公告)号：EP1428220A2

    公开(公告)日：2004-06-16

    申请号：EP02773439.1

    申请日：2002-09-17

    Applicant: SanDisk Corporation

    Inventor： CERNEA, Raul, Adrian

    IPC: G11C7/10

    CPC classification number: G11C7/1048 ,  G11C7/1036 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087

    Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables a different selecting circuit in sequence. That particular selecting circuit that has been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuit will send the stored information through to the output buffer for output from the integrated circuit. And while in a programming mode, the selected selecting circuit will receive data from an input buffer. This data will be written into a memory cell.

    MEMORY DEVICE AND DATA PROCESSING SYSTEM WITH SUCH A MEMORY DEVICE
    123.
    发明授权
    MEMORY DEVICE AND DATA PROCESSING SYSTEM WITH SUCH A MEMORY DEVICE 失效
    存储设备与数据处理系统，这样的存储设备

    公开(公告)号：EP0781443B1

    公开(公告)日：2000-05-10

    申请号：EP95935051.3

    申请日：1995-09-11

    Applicant: CIRRUS LOGIC, INC.

    Inventor： RAO, G., R., Mohan

    IPC: G09G1/16 ,  G09G5/36 ,  G11C7/00

    CPC classification number: G11C7/1036

    Abstract: A memory (200) is provided which includes a plurality of self-contained memory units (201) for storing data. A plurality of shift registers (211) are provided, each including a first parallel port coupled to a data port of a corresponding one of the self-contained memory units (201). Interconnection circuitry (212) is coupled to a parallel data port of each of the shift registers. Control circuitry (208, 213) is provided which is operable to control the exchange of data between a selected one of the memory units and the interconnection circuitry (212) via the shift register (211) coupled to the selected memory unit (201).

    Method and apparatus for accessing a parallel memory buffer with serial data
    124.
    发明公开
    Method and apparatus for accessing a parallel memory buffer with serial data 审中-公开
    用于访问并行存储缓冲器与串行数据的方法和装置

    公开(公告)号：EP0961435A2

    公开(公告)日：1999-12-01

    申请号：EP99108473.2

    申请日：1999-04-30

    Applicant: Siemens Information and Communication Networks Inc.

    Inventor： Cole, Steven R.

    IPC: H04J3/16

    CPC classification number: G11C7/1051 ,  G11C7/1036 ,  G11C7/1078 ,  H04J3/0626 ,  H04J3/1641

    Abstract: A memory buffer apparatus (29) includes an extended shift register (32) and a memory (30). The extended shift register (32) shifts a plurality of serial bits to produce a multi-bit data word. The multi-bit data word has a predetermined length based on a delay interval that is a multiple of a serial bit period. The memory (30) stores the bit-slice of the multi-bit data word. The bit-slice has a length less than that of the multi-bit data word. An extended output shift register (34) can also be included in the apparatus (29). The extended output shift register (34) has a length greater than the stored bit-slice, and performs a parallel-to-serial conversion of the bit-slice output from the memory (30).

    Abstract translation: 存储器缓冲设备（29）包括在延长的移位寄存器（32）和存储器（30）。 扩展移位寄存器（32）串行移位的多元化，以产生多比特数据字。 多比特数据字具有基于延迟间隔做了预定长度为一个串行比特周期的倍数。 所述存储器（30）存储所述多比特数据字的位片。 所述位片具有比所述多位数据字的更小的长度。 因此延长的输出移位寄存器（34）可以被包括在所述装置（29）。 扩展输出移位寄存器（34）的长度比所存储的位片更大，并且执行从存储器（30）输出的位片的并行到串行转换。

    Memory devices with selectable access type and systems and methods using the same
    126.
    发明公开
    Memory devices with selectable access type and systems and methods using the same 失效
    具有可选访问类型的存储器设备以及使用该设备的系统和方法

    公开(公告)号：EP0771007A2

    公开(公告)日：1997-05-02

    申请号：EP96307293.9

    申请日：1996-10-04

    Applicant: CIRRUS LOGIC, INC.

    Inventor： Rao, G.R. Mohan

    IPC: G11C7/00

    CPC classification number: G11C7/1036 ,  G11C7/1045

    Abstract: A memory 200 including an array 201 of rows and columns of memory cells. Row decoder circuitry 211 is provided for selecting in response to a row address a row in array 201 for access. Column decoder circuitry 205 is provided for selecting at least one location within a first group of columns along the selected row in array 201 in response to a column address. At least one shift register 207 is provided for allowing serial access to one of the cells within a second group of columns along the selected row.

    Abstract translation: 存储器200包括存储器单元的行和列的阵列201。 行解码器电路211被提供用于响应于行地址选择阵列201中的行以进行访问。 列解码器电路205被提供用于响应于列地址来选择沿着阵列201中的所选行的第一组列中的至少一个位置。 提供至少一个移位寄存器207，用于允许沿着所选择的行对第二组列中的一个单元进行串行访问。

    Semiconductor memory device
    127.
    发明公开
    Semiconductor memory device 失效
    Halbleiterspeicheranordnung。

    公开(公告)号：EP0590953A2

    公开(公告)日：1994-04-06

    申请号：EP93307716.6

    申请日：1993-09-29

    Applicant: NEC CORPORATION

    Inventor： Okimura, Yasunori, c/o NEC IC Microcomp. Syst. Ltd

    IPC: G11C7/00

    CPC classification number: G11C7/1036

    Abstract: A semiconductor memory circuit includes a memory cell array for storing data, and a bit structure selection circuit for performing a data transfer between the memory cell array and an external device by constructing the data in units of one bit or in units of two bits. The bit structure selection circuit includes a selector for selectively modifying a phase of a first clock signal and a second clock signal in response to a mode signal, and shift register for modifying a shift width of a memory selection signal in response to the first clock signal and the second clock signal supplied through the selector.

    Abstract translation: 半导体存储器电路包括用于存储数据的存储单元阵列，以及位结构选择电路，用于通过以1位为单位或以2位为单位构造数据来执行存储单元阵列与外部设备之间的数据传输。 比特结构选择电路包括：选择器，用于响应于模式信号选择性地修改第一时钟信号和第二时钟信号的相位;以及移位寄存器，用于响应于第一时钟信号修改存储器选择信号的移位宽度 以及通过选择器提供的第二时钟信号。

    Video memory
    128.
    发明公开
    Video memory 失效
    Videospeicher。

    公开(公告)号：EP0249985A2

    公开(公告)日：1987-12-23

    申请号：EP87108801.9

    申请日：1987-06-19

    Applicant: SONY CORPORATION

    Inventor： Ebihara, Norio ,  Sasaki, Takayuki ,  Kita, Hiroyuki ,  Ohsawa, Yoshihito

    IPC: H04N5/907

    CPC classification number: G11C7/1036 ,  H04N5/907 ,  H04N9/877

    Abstract: A video memory, for use with a video tape recorder, a television receiver of the like to process a picture, is simplified and can achieve the functions of a time base corrector, a noise reduced and a comb filter, so as to considerably improve the quality of a video picture. A frequency converting circuit for use with the video memory includes a comparator (30) for comparing first and second address signals and an address correction circuit (38) connected to receive an output signal from the com­parator (30). When a crossing occurs between the first and second address signals, the sequential order in which an address signal is supplied to the memory (12) is switched by the address correcting circuit (38), to thereby derive a continuous output signal from the memory (12).

    Abstract translation: 与视频磁带录像机一起使用的视频存储器，用于处理图像的电视接收机被简化，并且可以实现时基校正器，降噪和梳状滤波器的功能，从而显着改善 视频图片的质量。 与视频存储器一起使用的频率转换电路包括用于比较第一和第二地址信号的比较器（30）和被连接以从比较器（30）接收输出信号的地址校正电路（38）。 当在第一和第二地址信号之间发生交叉时，由地址校正电路（38）切换地址信号提供给存储器（12）的顺序，从而从存储器（43）中导出连续的输出信号 12）。

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