公开(公告)号：US09627289B2

公开(公告)日：2017-04-18

申请号：US14964121

申请日：2015-12-09

Applicant: J-Devices Corporation

Inventor： Yoshihiko Ikemoto ,  Shigenori Sawachi ,  Fumihiko Taniguchi ,  Akio Katsumata

IPC: H01L23/473 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L23/552 ,  H01L23/498

CPC classification number: H01L23/3142 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5227 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267

Abstract: The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the RF circuit of the semiconductor device is improved even using the metal flat plate as a support.

公开(公告)号：US09601450B2

公开(公告)日：2017-03-21

申请号：US14669491

申请日：2015-03-26

Applicant: J-DEVICES CORPORATION

Inventor： Takeshi Miyakoshi ,  Sumikazu Hosoyamada ,  Yoshikazu Kumagaya ,  Tomoshige Chikai ,  Shingo Nakamura ,  Hiroaki Matsubara ,  Shotaro Sakumoto

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/36 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3142 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29191 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/43

Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

公开(公告)号：US20160351511A1

公开(公告)日：2016-12-01

申请号：US15235439

申请日：2016-08-12

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki HASHIMOTO ,  Yasuyuki TAKEHARA

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0224 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.

公开(公告)号：US20160233141A1

公开(公告)日：2016-08-11

申请号：US15018563

申请日：2016-02-08

Applicant: J-DEVICES CORPORATION

Inventor： Masao HIROBE

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/3675 ,  H01L23/04 ,  H01L23/10 ,  H01L23/3736 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13101 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/059 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/16153 ,  H01L2924/1616 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0655 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/0635 ,  H01L2924/0675 ,  H01L2924/00

Abstract: There is provided a semiconductor device including a substrate whose surface is made of an insulation material, a semiconductor chip flip-chip connected on the substrate, and a heat sink bonded to the semiconductor chip via a thermal interface material and fixed to the substrate outside the semiconductor chip, in which the heat sink has a protrusion part protruding toward the substrate and bonded to the substrate via a conductive resin between a part bonded to semiconductor chip and a part fixed to the substrate and the heat sink has a stress absorbing part. According to the present invention, the protrusion part of the heat sink is prevented from being peeled off from the substrate at the part where the protrusion part of the heat sink is bonded to the substrate.

Abstract translation: 提供了一种半导体器件，其包括其表面由绝缘材料制成的衬底，连接在衬底上的半导体芯片倒装芯片和经由热界面材料接合到半导体芯片的散热器，并且固定到衬底外部的衬底 半导体芯片，其中散热器具有突出部分，突出部分朝向基板突出并且通过导电树脂在接合到半导体芯片的部件和固定到基板的部件之间并且散热器接合到基板上，具有应力吸收部分。 根据本发明，防止散热器的突起部在散热片的突出部分接合到基板的部分处从基板剥离。

公开(公告)号：US20160225701A1

公开(公告)日：2016-08-04

申请号：US15010988

申请日：2016-01-29

Applicant: J-DEVICES CORPORATION

Inventor： Yoshihiro TANAKA

IPC: H01L23/495

CPC classification number: H01L23/49513 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/26175 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/29078 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83048 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83815 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device according to one embodiment of the present invention includes a semiconductor element, an island having a surface on which the semiconductor element is fixed using a first metal, and a first pattern formed by a second metal, the first pattern being arranged on one part of the surface, wherein the second metal has a greater wetting characteristic than the surface when the first metal is melted.

Abstract translation: 根据本发明的一个实施例的半导体器件包括半导体元件，具有使用第一金属固定半导体元件的表面的岛和由第二金属形成的第一图案，第一图案被布置在一个上 表面的一部分，其中当第一金属熔化时，第二金属具有比表面更大的润湿特性。

公开(公告)号：US09368474B2

公开(公告)日：2016-06-14

申请号：US14850589

申请日：2015-09-10

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki Matsubara ,  Tomoshige Chikai ,  Kiminori Ishido ,  Takashi Nakamura ,  Hirokazu Honda ,  Hiroshi Demachi ,  Yoshikazu Kumagaya ,  Shotaro Sakumoto ,  Shinji Watanabe ,  Sumikazu Hosoyamada ,  Shingo Nakamura ,  Takeshi Miyakoshi ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L21/56 ,  H01L21/304

CPC classification number: H01L24/96 ,  H01L21/3043 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness.

Abstract translation: 本发明的半导体装置的制造方法包括：准备包含形成在其中的电极的半导体晶片; 将形成在半导体芯片中的第一半导体元件和形成在半导体晶片中的电极电连接; 用第一绝缘树脂层填充半导体晶片和半导体芯片之间的间隙; 在半导体晶片上形成第二绝缘树脂层; 研磨第二绝缘树脂层和半导体芯片直到半导体芯片的厚度达到预定厚度; 在所述第二绝缘树脂层和所述半导体芯片上形成第一绝缘层; 在与填充有第一绝缘层和第二绝缘树脂层的开口的导电材料连接的第一绝缘层上形成线以露出电极; 并研磨半导体晶片直到半导体晶片的厚度达到预定厚度。

公开(公告)号：US20150279759A1

公开(公告)日：2015-10-01

申请号：US14669491

申请日：2015-03-26

Applicant: J-DEVICES CORPORATION

Inventor： Takeshi Miyakoshi ,  Sumikazu HOSOYAMADA ,  Yoshikazu KUMAGAYA ,  Tomoshige CHIKAI ,  Shingo NAKAMURA ,  Hiroaki MATSUBARA ,  Shotaro SAKUMOTO

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3142 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29191 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/43

Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

Abstract translation: 实施例中的叠层半导体封装包括：第一半导体封装，包括第一电路板和安装在第一电路板上的第一半导体元件; 以及第二半导体封装，包括安装在第二电路板上的第二电路板和第二半导体元件，第二半导体封装堆叠在第一半导体封装上。 第一半导体封装还包括密封第一半导体元件的密封树脂; 与所述密封树脂接触的导电层; 以及连接到导电层并位于第一电路板上的热通孔。

公开(公告)号：US09093393B2

公开(公告)日：2015-07-28

申请号：US14083834

申请日：2013-11-19

Applicant: J-DEVICES CORPORATION

Inventor： Toru Suda

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/14 ,  H01L23/556 ,  H01L23/498

CPC classification number: H01L23/3157 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/556 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/11462 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a rectangular lower semiconductor element; a plurality of external electrodes located in a pattern on the lower semiconductor element along sides thereof; a plurality of internal electrodes electrically connected to the plurality of external electrodes via a plurality of line patterns respectively and located on the lower semiconductor element in a pattern; dams provided in such a pattern that each of the dams encloses one or at least two external electrodes among the plurality of external electrodes; an upper semiconductor element mounted on the lower semiconductor element such that a plurality of terminals on the upper semiconductor element are electrically connected to the plurality of internal electrodes respectively; and a resin potted to flow to a space between the lower semiconductor element and the upper semiconductor element.

Abstract translation: 半导体器件包括矩形下半导体元件; 多个外部电极，沿其侧面位于下部半导体元件上的图案中; 多个内部电极经由多个线图案电连接到所述多个外部电极，并以图案位于所述下部半导体元件上; 堤坝以这样的图案提供，使得每个坝围绕多个外部电极中的一个或至少两个外部电极; 上半导体元件，其安装在所述下半导体元件上，使得所述上半导体元件上的多个端子分别电连接到所述多个内部电极; 以及被封装以流到下半导体元件和上半导体元件之间的空间的树脂。