公开(公告)号：US20160351511A1

公开(公告)日：2016-12-01

申请号：US15235439

申请日：2016-08-12

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki HASHIMOTO ,  Yasuyuki TAKEHARA

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0224 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.

公开(公告)号：US20160172265A1

公开(公告)日：2016-06-16

申请号：US14944480

申请日：2015-11-18

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki HASHIMOTO

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/83

Abstract: A semiconductor package includes a first semiconductor device provided on a support substrate; a first encapsulation material covering the first semiconductor device; a first line provided on the first encapsulation material, the first line being connected with the first semiconductor device; an intermediate buffer layer covering the first line, and a second encapsulation material provided on the intermediate buffer layer. The first encapsulation material and the second encapsulation material are each formed of an insulating material different from an insulating material used to form the intermediate buffer layer. A second semiconductor device covered with the second encapsulation material may be provided on the intermediate buffer layer.

Abstract translation: 半导体封装包括设置在支撑基板上的第一半导体器件; 覆盖所述第一半导体器件的第一封装材料; 设置在所述第一封装材料上的第一线，所述第一线与所述第一半导体器件连接; 覆盖第一线的中间缓冲层和设置在中间缓冲层上的第二封装材料。 第一封装材料和第二封装材料均由与用于形成中间缓冲层的绝缘材料不同的绝缘材料形成。 覆盖有第二封装材料的第二半导体器件可以设置在中间缓冲层上。

公开(公告)号：US20170207157A1

公开(公告)日：2017-07-20

申请号：US15375241

申请日：2016-12-12

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki HASHIMOTO ,  Yuko YAMAMOTO

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/30 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2224/29195 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511

Abstract: A method for manufacturing a semiconductor package includes: forming an insulating layer on a support plate; forming a via in the insulating layer; locating a semiconductor device on the insulating layer such that an electrode of the semiconductor device is on the via; removing the support plate; forming a seed layer on a surface of the insulating layer opposite to the semiconductor device, in the via, and on a surface of the electrode of the semiconductor device; and forming a metal layer in the via.

公开(公告)号：US20150371915A1

公开(公告)日：2015-12-24

申请号：US14739829

申请日：2015-06-15

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki HASHIMOTO ,  Yasuyuki TAKEHARA

IPC: H01L23/31 ,  H01L23/544 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0224 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.

Abstract translation: 半导体封装包括支撑衬底; 设置在所述支撑基板的主表面上的应力松弛层; 位于应力松弛层上的半导体器件; 覆盖半导体器件的封装材料，封装材料由与应力松弛层不同的绝缘材料形成; 穿过封装材料并电连接到半导体器件的线; 以及与该线路电连接的外部端子。 在支撑基板具有A的弹性模量的情况下，应力松弛层的弹性模量为B，封装材料在相同的温度条件下具有C的弹性模量，A> C> B或C> A的关系 > B。