Abstract:
A built-in receiver self-test system provides on-chip testing with minimal change to the receiver footprint. The system digitally generates a two-tone test signal, and tests the nonlinearities of the receiver using the generated two-tone test signal. To that end, the self-test system comprises a stimulus generator, a downconverter, and a demodulator, all of which are disposed on a common receiver chip. The stimulus generator generates a test signal comprising first and second tones at respective first and second frequencies, where the first and second frequencies are spaced by an offset frequency, and where the first frequency comprises a non-integer multiple of the offset frequency. The downcoverter downconverts the test signal to generate an In-phase component and a Quadrature component. The demodulator measures an amplitude of the intermodulation tone by demodulating the In-phase and Quadrature components based on a reference frequency.
Abstract:
According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of α*I and the second current has a magnitude of β*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (α−β)*I.
Abstract:
A current-mode regulator relies on indirect current measurement to facilitate slope compensation used to stabilize the operation of a buck converter. The current-mode regulator comprises an inductor, a switching network, and a controller. The inductor delivers an output current to a load. The switching network selectively connects the inductor input to an input voltage or a second voltage. The regulator controls the switching network. An inner loop control circuit of the regulator comprises the switching network, a current measuring circuit, a slope circuit, a comparator, and a switching controller. The current measuring circuit comprises a passive network connected to the inductor input and operative to indicate an inductor current as a measurement voltage. The slope circuit applies a time-varying voltage having a positive slope to the measurement voltage. The comparator compares a slope compensated measurement voltage to the control voltage. The switching regulator controls the switching network in response to the output of the comparator.
Abstract:
Systems and methods are provided for authenticating Internet Protocol (IP) Multimedia Subsystem (IMS) applications in a User Equipment (UE). A method includes: receiving a first Session Initiation Protocol (SIP) REGISTER message from an IMS application operating on the UE; transmitting a response message to the IMS application based on the received first SIP REGISTER message; receiving a second SIP REGISTER message from the IMS application operating on the UE; determining authentication for the IMS application based on the received second SIP REGISTER message from the IMS application operating on the UE; and based on the step of determining authentication for the IMS application, if the IMS application is authorized, then transmitting information associated with the first and second SIP REGISTER messages toward a SIP node or if the IMS application is unauthorized, then discarding data associated with the first and second SIP REGISTER messages.
Abstract:
Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.
Abstract:
Methods of configuring dynamic memory associated with a processing system, are described. The dynamic memory is configured in a plurality of blocks, the method comprises: a) receiving information relating to a utilization status of the memory; b) processing the received information to determine at least one first block of the memory that is currently not in use for information storage; and c) configuring the at least one first block to be excluded from an information refresh process.
Abstract:
A method permits a UE receiver to detect and report to the network a scrambling code collision (i.e., two neighbor cells transmitting with the same scrambling code while timing is aligned). The UE receiver decodes the PCCPCH's physical channel with all the associated broadcast information while a scrambling code collision at the UE is present. The UE reports SFN-SFN information to the network, to insure the UE mobility and then prepare the handover to a new detected cell. This process and a respective apparatus are usable in the presence of MIMO and further improve the detection of the scrambling code collision in the presence of MIMO.
Abstract:
There is described a charge pump circuit (1) circuit comprising an input terminal, an output terminal (5) connected to an intermediate node (Ni), a ground terminal (4), a first fly capacitor module (21) with a first fly capacitor (Cfly1) having a first pin (211) and a second pin (212) and connected to the intermediate node (Ni); and a second fly capacitor module (22) with a first fly capacitor (Cfly2) having a first pin (221) and a second pin (222) and connected to the intermediate node (Ni); wherein each being adapted to successively charge and discharge a the first fly capacitor and the second fly capacitor, respectively, wherein the second pin (212) of the first fly capacitor module (21) is connected to the first pin (221) of the second fly capacitor module (22) by a direct connection.
Abstract:
A method of determining a calibration of a near field communication, NFC, device, the NFC device comprising a receiver circuit, a transmitter circuit and a load modulator circuit, the method comprising: generating a carrier signal in the transmitter circuit, generating a modulation signal in the load modulator circuit, generating a modulated carrier signal, comprising first and second frequencies, by applying the modulation signal to the carrier signal, applying the modulated carrier signal at an input of the receiver circuit, and determining a response parameter of the receiver circuit on the basis of the response of the receiver circuit to the first and second frequencies in the modulated carrier signal.
Abstract:
An emitter for modulating and emitting an orthogonal frequency division multiplexing signal through a transmission channel (TC), comprising a frequency-to-time converter for converting symbols to be transmitted into time symbols, and means for serializing and amplifying said time symbol so as to emit it as an OFDM signal through said transmission channel, said emitter further comprising: means (12) for clipping said time symbols; time-to-frequency convertor (13) for converting said time symbols; and means for applying a set of data subcarriers of the outputs of said time-to-frequency converter as inputs of said frequency-to-time converter wherein out-of-band subcarriers are set to zero and the clipping level is set to a minimum level allowing the amplifier to operate in an efficient region.