公开(公告)号：KR100541555B1

公开(公告)日：2006-01-11

申请号：KR1020040019007

申请日：2004-03-19

Applicant: 삼성전자주식회사

Inventor： 박재현 ,  김형준 ,  정원철 ,  정창욱

IPC: G11C11/15

Abstract: 도금층으로 둘러싸인 분할된 서브 디지트 라인들을 갖는 자기 램 셀들 및 그 제조방법들이 제공된다. 상기 자기 램 셀들은 반도체기판 상부에 형성된 제1 및 제2 서브 디지트 라인들을 구비한다. 상기 제1 서브 디지트 라인의 하부면 및 상기 제1 서브 디지트 라인의 상기 하부면에 인접하면서 상기 제2 서브 디지트 라인의 반대편에 위치하는 외측벽(outer sidewall)은 제1 도금층 패턴으로 덮여진다. 이와 마찬가지로, 상기 제2 서브 디지트 라인의 하부면 및 상기 제2 서브 디지트 라인의 상기 하부면에 인접하면서 상기 제1 서브 디지트 라인의 반대편에 위치하는 외측벽은 제2 도금층 패턴으로 덮여진다. 상기 제1 및 제2 서브 디지트 라인들 및 상기 제1 및 제2 도금층 패턴들은 층간절연층 내에 그루브를 형성하고, 상기 그루브의 측벽들 및 바닥면을 덮는 도금층 패턴과 아울러서 상기 도금층 패턴에 의해 둘러싸여진 공간을 채우는 디지트 라인을 형성하고, 상기 디지트 라인 및 도금층 패턴을 패터닝함으로써 형성된다.

公开(公告)号：KR1020050054397A

公开(公告)日：2005-06-10

申请号：KR1020030087771

申请日：2003-12-04

Applicant: 삼성전자주식회사

Inventor： 김형준

IPC: G06F15/16

Abstract: 본 발명은 네트웍 관리 인터페이스 제공 방법에 관한 것으로, 특히 TL-1을 이용한 원격 장비관리에 있어서 통신 네트웍 계층과 무관하게 데이터 송수신이 가능하도록 함으로써 네트웍을 관리할 수 있도록 하는 네트웍 관리 방법에 관한 것이다. 본 발명은 관리정보를 물리적으로 전송하는 하위 전송 계층에 의존적이지 않고, 외부 관리장비에게 올바른 해당 NE 의 관리 정보를 제공하기 위한 메시지를 목적지 NE 의 프락시(proxy)타스크에서 처리하도록 함으로써 효율적으로 NE 를 관리할 수 있도록 하였다. 이에 따라 별개의 통신 시스템에 대해서도 최소의 작업만으로 매니지먼트 인터페이스 적용이 가능하게 되었다.

公开(公告)号：KR1020050029424A

公开(公告)日：2005-03-28

申请号：KR1020030065680

申请日：2003-09-22

Applicant: 삼성전자주식회사

Inventor： 김형준 ,  김승범 ,  박원모 ,  권준모

IPC: H01L21/28

Abstract: A method of forming a semiconductor device including landing pads is provided to restrain damage of an interlayer dielectric in a cleaning process by preventing exposure of a wiring contact hole in a process for forming a wiring contact hole. A plurality of parallel gate patterns are formed on a semiconductor substrate(20). Each of the parallel gate patterns includes a lamination of a gate insulating layer(22), a gate electrode(23), and a mask insulating layer(24). A plurality of insulating layer spacers(25) are formed to cover sidewalls of the gate patterns. A first interlayer dielectric(26) is formed on the semiconductor substrate by using a material layer having etch selectivity to the mask insulating layers and the insulating layer spacers. A self-aligned contact hole is formed by patterning the first interlayer dielectric. A landing pad(27a) is formed to fill the self-aligned contact hole. Each upper surface of the mask insulating layers is exposed by etching back the first interlayer dielectric. A second interlayer dielectric(28) is formed on the semiconductor substrate. A wiring contact hole(28a) is formed by patterning the second interlayer dielectric.

Abstract translation: 提供一种形成包括着陆焊盘的半导体器件的方法，以通过在形成布线接触孔的过程中防止布线接触孔的暴露来抑制清洁过程中的层间电介质的损坏。 在半导体衬底（20）上形成多个平行栅极图案。 每个平行栅极图案包括栅极绝缘层（22），栅电极（23）和掩模绝缘层（24）的叠层。 形成多个绝缘层间隔物（25）以覆盖栅极图案的侧壁。 通过使用对掩模绝缘层和绝缘层间隔物具有蚀刻选择性的材料层，在半导体衬底上形成第一层间电介质（26）。 通过图案化第一层间电介质形成自对准接触孔。 形成着陆垫（27a）以填充自对准的接触孔。 掩模绝缘层的每个上表面通过蚀刻回第一层间电介质而暴露。 在半导体衬底上形成第二层间电介质（28）。 通过图案化第二层间电介质形成布线接触孔（28a）。

公开(公告)号：KR1020030061147A

公开(公告)日：2003-07-18

申请号：KR1020020001678

申请日：2002-01-11

Applicant: 삼성전자주식회사

Inventor： 김형준

IPC: H04L12/44

Abstract: PURPOSE: An alarm masking method using a tree-type hierarchical structure and a recorded medium therefor are provided to perform an alarm masking process for a generated alarm, and to stratify an alarm masking hierarchical structure, thereby managing the alarm at a high speed as well as improving system performance. CONSTITUTION: A system moves to a fault node(S1), and decides whether a child node exists(S2). If so, the system moves to another fault node, and decides whether a child node exists in the fault node(S2). If so, the system moves to another fault node(S3). The system decides whether a child node exists in the fault node(S2). If not, the system decides whether the corresponding node is a desirous node(S4). If not, the system decides whether a sibling node exists(S5). If so, the system moves to another fault node(S6). If the sibling node does not exist, the system moves to the fault node which is a parent node(S7).

Abstract translation: 目的：提供一种使用树型分层结构的报警屏蔽方法及其记录介质，以对所产生的报警进行报警屏蔽处理，并分层报警屏蔽层次结构，从而高速管理报警 提高系统性能。 构成：系统移动到故障节点（S1），并决定是否存在子节点（S2）。 如果是，则系统移动到另一个故障节点，并判断故障节点中是否存在子节点（S2）。 如果是，系统移动到另一个故障节点（S3）。 系统决定故障节点中是否存在子节点（S2）。 如果不是，则系统判定对应的节点是否是希望节点（S4）。 如果不是，系统决定是否存在兄弟节点（S5）。 如果是，系统移动到另一个故障节点（S6）。 如果兄弟节点不存在，则系统移动到作为父节点的故障节点（S7）。

公开(公告)号：KR3003275990000S

公开(公告)日：2003-06-28

申请号：KR3020020021833

申请日：2002-07-30

Applicant: 삼성전자주식회사

Designer： 김형준

公开(公告)号：KR3003276010000S

公开(公告)日：2003-06-27

申请号：KR3020020021832

申请日：2002-07-30

Applicant: 삼성전자주식회사

Designer： 김형준

公开(公告)号：KR1020030047076A

公开(公告)日：2003-06-18

申请号：KR1020010077458

申请日：2001-12-07

Applicant: 삼성전자주식회사

Inventor： 김형준

IPC: H01L21/205

Abstract: PURPOSE: A CVD(Chemical Vapor Deposition) equipment having a latch for locking a boat and a method for manufacturing a semiconductor device using the same are provided to be capable of preventing the generation of particles by improving the connecting state between a boat and a boat cap by using a latch. CONSTITUTION: A CVD equipment is provided with cylindrical heater part, an outer tube having a closed upper portion located in the heater part, an inner tube having an opened upper portion located in the outer tube, a boat loaded into the inner tube, and a loader part having a boat cap(100) capable of loading the boat on the upper portion of the boat cap. The boat cap(100) further includes a plurality of fixing pins(110,120) and a latch(112) formed at the fixing pin(110) for completely locking the boat and boat cap. Preferably, the fixing pins are located at the edge portion of the boat cap.

Abstract translation: 目的：提供具有用于锁定船的闩锁的CVD（化学气相沉积）设备以及使用其的制造半导体器件的方法，以能够通过改善船和船之间的连接状态来防止颗粒的产生 帽通过使用闩锁。 构成：CVD设备设置有圆柱形加热器部分，外管具有位于加热器部分中的封闭上部，内管具有位于外管中的开口上部，装载到内管中的船，和 装载器部件具有能够将船体装载在船帽上部的船盖（100）。 船盖（100）还包括形成在固定销（110）处的多个固定销（110,120）和闩锁（112），用于完全锁定船和船盖。 优选地，固定销位于船帽的边缘部分。

公开(公告)号：KR100383325B1

公开(公告)日：2003-05-12

申请号：KR1020010003066

申请日：2001-01-19

Applicant: 삼성전자주식회사

Inventor： 김형준 ,  박영욱 ,  남병윤

IPC: H01L27/10

CPC classification number: H01L21/76831 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: The present invention provide integrated circuit devices and methods of fabricating the same that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract translation: 本发明提供集成电路器件及其制造方法，其包括微电子衬底和设置在微电子衬底上的导电层。 绝缘层设置在导电层上，并且绝缘层包括延伸超过导电层的悬垂部分。 侧壁绝缘区横向地邻近导电层的侧壁设置并且在绝缘层的悬垂部分和微电子衬底之间延伸。

公开(公告)号：KR100376135B1

公开(公告)日：2003-03-15

申请号：KR1020010000636

申请日：2001-01-05

Applicant: 삼성전자주식회사

Inventor： 김형준

IPC: H04L12/26

Abstract: PURPOSE: A method for controlling the availability management of an integrated service digital user part is provided to enable an ASS-7 block to transmit a UPU message in only case that all ASP is abnormal, thereby preventing transmission drop due to the state change of one ASP. CONSTITUTION: An INS(Interconnection Network Subsystem) inquires about the availability of a UPC(User Part Control) block to each ASP(Access Switch Processor)(40). Each ASP responses to the INS(41). It is determined whether each ASP responses(42). If responses, the UPC block of each ASP is normally managed(43). If not response, each ASP is updated(44). The update management state of each ASP is transmitted to an MTP(Message Transfer Part) of an ASS(Access Switch Subsystem)- 7(45). It is determined whether all ASP does not response(46). A UPU(User Part Unavailable) message is transmitted to a remote station through the MTP(47).

Abstract translation: 目的：提供一种用于控制综合业务数字用户部分的可用性管理的方法，以使ASS-7模块能够在所有ASP不正常的情况下发送UPU消息，从而防止由于一个ASP ASP。 构成：INS（互连网络子系统）向每个ASP（接入交换机处理器）（40）查询UPC（用户部分控制）块的可用性。 每个ASP响应INS（41）。 确定每个ASP响应（42）。 如果是响应，每个ASP的UPC块通常被管理（43）。 如果没有响应，则更新每个ASP（44）。 每个ASP的更新管理状态被发送到ASS（接入交换子系统）-7（45）的MTP（消息传送部分）。 确定所有ASP是否不响应（46）。 UPU（用户部分不可用）消息通过MTP（47）发送到远程站。

公开(公告)号：KR100366621B1

公开(公告)日：2003-01-09

申请号：KR1020000035950

申请日：2000-06-28

Applicant: 삼성전자주식회사

Inventor： 김지수 ,  추창웅 ,  김동현 ,  오용철 ,  김형준 ,  남병윤 ,  박경원 ,  이상협

IPC: H01L21/28

CPC classification number: H01L21/76897 ,  H01L21/76801 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.

Abstract translation: 提供了使用伪介电层来导电地接触其上包括多个间隔开的线的集成电路的方法。 在第一选择的间隔线之间形成伪介电层。 在间隔开的第二行中不同于第一次选择的行之间形成中间介电层。 相对于预定的蚀刻剂，中间介电层具有比伪介电层更低的蚀刻速率。 用预定的蚀刻剂蚀刻伪介电层，以去除第一选定的间隔线之间的至少一些伪介电层。 导电层形成在间隔开的线的第一选定线之间，至少一些伪介电层已从第一选择线移除，以在第一选定间隔线之间与集成电路电接触。