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公开(公告)号：KR1020040040846A
公开(公告)日：2004-05-13
申请号：KR1020020069169
申请日：2002-11-08
Applicant: 한국전자통신연구원
IPC: G06K19/077
Abstract: PURPOSE: An active RFID(Radio Frequency Identification) tag is provided to perfectly perform an RFID function, comprise a simple circuit, and adapt to a conventional information communication terminal by simply modifying hardware and a program. CONSTITUTION: An analog signal processor(220) restores a clock from a carrier signal received through an antenna(210), demodulates an RF signal received through the antenna, and modulates a transmitting signal. A DSP(Digital Signal Processor)(230) generates a transmitting/receiving reference clock by demodulating the clock received from the analog signal processor, restricts transmitting operation while the analog data processor receives data, and modulates/transfers the transmitting data to the analog signal processor. A logical operator(240) performs communication with an external device according to a predetermined protocol. A power supply(250) supplies power to each component.
Abstract translation: 目的：提供有源RFID（射频识别）标签以完美地执行RFID功能，包括简单的电路，并通过简单地修改硬件和程序来适应传统的信息通信终端。 构成：模拟信号处理器（220）从通过天线（210）接收的载波信号恢复时钟，解调通过天线接收的RF信号，并调制发射信号。 DSP（数字信号处理器）（230）通过解调从模拟信号处理器接收的时钟来产生发送/接收参考时钟，在模拟数据处理器接收数据时限制发送操作，并且将发送数据调制/传送到模拟信号 处理器。 逻辑运算符（240）根据预定协议与外部设备进行通信。 电源（250）为每个组件供电。
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公开(公告)号：KR1020040040060A
公开(公告)日：2004-05-12
申请号：KR1020020068377
申请日：2002-11-06
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A device and a method for controlling an electronic device using a wireless media are provided to control the electronic device linked with various kinds of non-contact typed electronic money IC cards. CONSTITUTION: A communicator(130) recognizes the non-contact typed electronic card(180) and performs wireless communication. A charge/time calculator(150) calculates an available view time according to a desired view time or a view charge by receiving the desired view time or the view charge of a user. A security processor(170) executes a certification function with the non-contact typed electronic card and stores transaction information. A controller(120) decides connection to the electronic device based on a calculating result of the charge/time calculator.
Abstract translation: 目的：提供一种使用无线介质控制电子装置的装置和方法，以控制与各种非接触式电子货币IC卡连接的电子装置。 构成：通信器（130）识别非接触型电子卡（180）并执行无线通信。 充电/时间计算器（150）通过接收期望的观看时间或用户的观看费用，根据期望的观看时间或观看费用来计算可用的观看时间。 安全处理器（170）使用非接触型电子卡执行认证功能并存储交易信息。 控制器（120）基于充电/时间计算器的计算结果确定与电子设备的连接。
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公开(公告)号：KR100406137B1
公开(公告)日：2003-11-14
申请号：KR1020010074630
申请日：2001-11-28
Applicant: 한국전자통신연구원
IPC: H04L9/14
Abstract: PURPOSE: A high-speed hardware cryptographic processing system and a method thereof are provided to enhance the performance of a cryptographic process by performing a symmetric key and an asymmetric key ciphering algorithm in parallel. CONSTITUTION: A scheduler(120) is used for generating the scheduling information for an executing procedure of a ciphering algorithm. A storage portion(130) stores rearranged command, rearrangement information, and the address information of the cryptographic data according to the scheduling information. A cryptographic processing portion(150) reads the stored data of the storage portion and performs a cryptographic process according to the command priority by referring to the command rearrangement information and the address information. A control portion(140) outputs a command to generate the scheduling information, sort cryptographic data, assign the data, and perform the cryptographic process.
Abstract translation: 目的：提供一种高速硬件密码处理系统及其方法，通过并行执行对称密钥和非对称密钥加密算法来增强密码处理的性能。 构成：调度器（120）用于生成加密算法的执行过程的调度信息。 存储部分（130）根据调度信息存储重排的命令，重排信息和密码数据的地址信息。 密码处理部分（150）读取存储部分的存储数据，并通过参考命令重排信息和地址信息根据命令优先级执行密码处理。 控制部分（140）输出生成调度信息的命令，对密码数据进行排序，分配数据，并执行密码处理。
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公开(公告)号：KR1020030048632A
公开(公告)日：2003-06-25
申请号：KR1020010078588
申请日：2001-12-12
Applicant: 한국전자통신연구원
IPC: G09C1/00
CPC classification number: H04L9/0625 , H04L2209/125 , H04L2209/24
Abstract: PURPOSE: An encryption device using a Kasumi encryption algorithm is provided to reduce the power consumption by forming around circuit with an FO block and an F1 block. CONSTITUTION: A register portion(100) stores selectively one of plaintext data and input data. A secret key scheduler(150) generates a secret key to encrypt the plaintext data. An FL block(160) is used for calculating output data of the register portion and the secret key by using an FL function of a Kasumi encryption algorithm. An FO block(170) the output data of the register portion and the secret key by using an F1 function of the Kasumi encryption algorithm. An adder portion(180A) performs an exclusive logical OR operation for each output data of the FO block and the F1 block and the output data of the register portion. An input/output control portion(200A) selects the input data of the FO block and the F1 block and a path of the output data.
Abstract translation: 目的：提供使用Kasumi加密算法的加密设备，以通过与FO块和F1块形成围绕电路来降低功耗。 构成：寄存器部分（100）选择性地存储明文数据和输入数据之一。 秘密密钥调度器（150）生成秘密密钥来加密明文数据。 FL块（160）用于通过使用Kasumi加密算法的FL函数来计算寄存器部分和秘密密钥的输出数据。 通过使用Kasumi加密算法的F1函数，FO块（170）寄存器部分的输出数据和秘密密钥。 加法器部分（180A）对FO块和F1块的每个输出数据以及寄存器部分的输出数据执行异或逻辑或运算。 输入/输出控制部分（200A）选择FO块和F1块的输入数据以及输出数据的路径。
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公开(公告)号：KR1020030048631A
公开(公告)日：2003-06-25
申请号：KR1020010078587
申请日：2001-12-12
Applicant: 한국전자통신연구원
IPC: G09C1/00
Abstract: PURPOSE: An apparatus for encoding an elliptic curve is provided to enhance the security and the performance of electronic commercial transaction, electronic cash, identification and key management of an user, and an approval process system by using various elliptic curve protocols. CONSTITUTION: An elliptic curve encoding apparatus includes a register file portion(200), an elliptic curve processor calculation portion(400), an order comparator portion(500), an NAF(Non Adjacent Format) converter portion(100), and an elliptic curve processor control portion(300). The register file portion stores input data and output data to encode an elliptic curve. The elliptic curve processor calculation portion performs a calculation operation for the elliptic curve by using the stored data of the register file portion. The order comparator portion searches and compares the orders necessary for the calculation operation. The NAF converter portion supports the scalar multiplication calculation. The elliptic curve processor control portion generates a control signal to control a calculation operation mode of the elliptic curve processor.
Abstract translation: 目的：提供一种用于编码椭圆曲线的装置，以通过使用各种椭圆曲线协议来增强电子商务交易的安全性和性能，电子现金，用户的识别和密钥管理以及批准过程系统。 构成：椭圆曲线编码装置包括寄存器文件部分（200），椭圆曲线处理器计算部分（400），顺序比较器部分（500），NAF（非相邻格式）转换器部分（100）和椭圆曲线 曲线处理器控制部分（300）。 寄存器文件部分存储输入数据和输出数据以编码椭圆曲线。 椭圆曲线处理器计算部分通过使用寄存器文件部分的存储数据来执行椭圆曲线的计算操作。 订单比较器部分搜索并比较计算操作所需的订单。 NAF转换器部分支持标量乘法运算。 椭圆曲线处理器控制部分生成控制信号以控制椭圆曲线处理器的计算操作模式。
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Patent Agency Ranking
公开(公告)号：KR1020030042968A
公开(公告)日：2003-06-02
申请号：KR1020010073892
申请日：2001-11-26
Applicant: 한국전자통신연구원
IPC: G06K17/00
Abstract: PURPOSE: A boosting system for an IC card system and a control method thereof are provided to boost a voltage to a desired level in a short time by using an internal voltage in a case that a voltage higher than an internal operation voltage is needed when an IC card system is driven. CONSTITUTION: The circuit comprises a charge storage(130), a booster(150), switches(140, 141), and a switching controller(120). The charge storage(130) stores the power supplied by a power supplier. The booster(150) boosts the voltage, stored at the charge storage(130), to a desired level, and supplies the boosted voltage for the internal circuit of the IC card system. The switches(140, 141) store the power at the charge storage(130) or supply the power according to a switching control signal. The switching controller(120) transmits the switching control signal to the switches(140, 141) according to an operation mode of the internal circuit of the IC card system. The switching controller(120) determines whether the IC card system is in a simple operation mode or a high voltage operation mode in order to transmit the switching control signal, and detects the charge stored at the charge storage(130).
Abstract translation: 目的：提供一种用于IC卡系统的升压系统及其控制方法，用于在需要高于内部工作电压的电压的情况下通过使用内部电压在短时间内将电压提升到所需电平， IC卡系统被驱动。 构成：电路包括电荷存储器（130），升压器（150），开关（140,141）和开关控制器（120）。 充电存储器（130）存储由电源供应的电力。 升压器（150）将存储在电荷存储器（130）处的电压升高到期望的电平，并为IC卡系统的内部电路提供升压电压。 开关（140,141）将电力存储在电荷存储器（130）处，或者根据开关控制信号供电。 切换控制器（120）根据IC卡系统的内部电路的操作模式将切换控制信号发送到开关（140,141）。 切换控制器（120）确定IC卡系统是处于简单操作模式还是高电压操作模式，以便发送开关控制信号，并且检测存储在电荷存储器（130）中的电荷。
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公开(公告)号：KR1020030018307A
公开(公告)日：2003-03-06
申请号：KR1020010051963
申请日：2001-08-28
Applicant: 한국전자통신연구원
IPC: G06K19/07
Abstract: PURPOSE: A smart card is provided to satisfy the ISO/ICE 7816(international Organization for Standardization/International Electrotechnical Commission) as a contact standard and the ISO/ICE 14443 as a non-contact standard, and to enable a non-contact interface to generate a reset signal and a clock from a wireless signal of a card reader. CONSTITUTION: The smart card(1) includes a CPU(22), a memory(23) and a crypto module(21). The CPU(22) communicates with a system logic circuit(30) through a bus. The system logic circuit(30) intermediates the communication between the CPU(22) and the card reader connecting through a contact interface or a non-contact interface. The contact interface connects contact terminals(P1-P5) with the system logic circuit(30). The non-contact interface connects a non-contact antenna(26) with the system logic circuit(30). The non-contact interface includes the RFC(Radio Frequency Circuit)(40). The RFC(40) detects power, a reset signal, the clock and data(RFI-TX) from the signal received by the non-contact antenna(26), provides it to the system logic circuit(30), and provides the data(RFI-RX) from the system logical circuit(30) to the card reader.
Abstract translation: 目的：提供智能卡以满足作为联系标准的ISO / ICE 7816（国际标准化组织/国际电工委员会），ISO / ICE 14443作为非接触式标准，并使非接触式接口 从读卡器的无线信号产生复位信号和时钟。 构成：智能卡（1）包括CPU（22），存储器（23）和加密模块（21）。 CPU（22）通过总线与系统逻辑电路（30）通信。 系统逻辑电路（30）中介CPU（22）和通过接触接口或非接触式接口连接的读卡器之间的通信。 触点界面将触点端子（P1-P5）与系统逻辑电路（30）连接起来。 非接触式接口将非接触式天线（26）与系统逻辑电路（30）连接。 非接触式接口包括RFC（射频电路）（40）。 RFC（40）从非接触式天线（26）接收的信号中检测功率，复位信号，时钟和数据（RFI-TX），将其提供给系统逻辑电路（30），并提供数据 （RFI-RX）从系统逻辑电路（30）到读卡器。
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公开(公告)号：KR1020030018203A
公开(公告)日：2003-03-06
申请号：KR1020010051800
申请日：2001-08-27
Applicant: 한국전자통신연구원
IPC: G06K19/07
Abstract: PURPOSE: A smart card including a USB(Universal Serial Bus) interface function is provided to improve communication speed and compatibility of the smart card by offering the smart card having a fast bus line, a peripheral device bus line, and an input/output interface module have the USB interface function supporting a USB of a PC. CONSTITUTION: A smart chip includes a control block(202), a memory block(210), a clock generating block(212), a signal processing block(214) and an interface block(216). The control block(202) controls an operation of the signal processing block(214) based on a clock provided from the clock generating block(212). The memory block(210) comprises an SRAM, a ROM and an EEPROM(Electronically Erasable and Programmable ROM). The SRAM reads and writes contents according to the execution of a card. The ROM stores an operating program of the card. The EEPROM stores an application program of various kinds of smart cards. The signal processing block(214) processes a signal among the control block(202), the memory block(210) and the interface block(216) physically connecting with each other through an internal bus.
Abstract translation: 目的：提供包括USB（通用串行总线）接口功能的智能卡，通过提供具有快速总线，外围设备总线和输入/输出接口的智能卡来提高智能卡的通信速度和兼容性 模块具有支持PC的USB的USB接口功能。 构成：智能芯片包括控制块（202），存储块（210），时钟生成块（212），信号处理块（214）和接口块（216）。 控制块（202）基于从时钟生成块（212）提供的时钟来控制信号处理块（214）的操作。 存储器块（210）包括SRAM，ROM和EEPROM（电可擦除和可编程ROM）。 SRAM根据卡的执行读取和写入内容。 ROM存储卡的操作程序。 EEPROM存储各种智能卡的应用程序。 信号处理块（214）通过内部总线处理在物理上彼此连接的控制块（202），存储块（210）和接口块（216）之间的信号。
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公开(公告)号：KR100284587B1
公开(公告)日：2001-03-15
申请号：KR1019980052347
申请日：1998-12-01
Applicant: 한국전자통신연구원
IPC: G09C1/00
Abstract: 본 발명은 대칭키 암호의 라운드 회로에 관한 것으로서, F-함수 모듈을 키에 의한 XOR 연산 블록, 제 1 키종속 치환 블록, 왼쪽 순환 블록 및 제 2 키종속 치환 블록으로 구성된 제 1 키종속 처리 블록과, 제 1 키종속 치환 블록, 왼쪽 순환 블록 및 제 2 키종속 치환 블록으로 구성된 제 2 키종속 처리 블록과, S-함수 블록을 포함하도록 재구성하여, 상기 제 1 및 제 2 키종속 처리블록의 결과를 XOR 연산한 후, S-함수를 거쳐 최종 치환 P를 수행함으로써, 종래의 16단 라운드를 8단 라운드로 줄이고, 그에 따른 수행 시간을 줄이도록 하는 것을 특징으로 한다.
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