公开(公告)号：US10553675B2

公开(公告)日：2020-02-04

申请号：US15785627

申请日：2017-10-17

Applicant: Infineon Technologies AG

Inventor： Sebastian Schmidt ,  Donald Dibra ,  Oliver Hellmund ,  Peter Irsigler ,  Andreas Meiser ,  Hans-Joachim Schulze ,  Martina Seider-Schmidt ,  Robert Wiesner

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: In accordance with an embodiment of an integrated circuit, a cavity is buried in a semiconductor body below a first surface of the semiconductor body. An active area portion of the semiconductor body is arranged between the first surface and the cavity. The integrated circuit further includes a trench isolation structure configured to provide a lateral electric isolation of the active area portion.

公开(公告)号：US10546920B2

公开(公告)日：2020-01-28

申请号：US15902158

申请日：2018-02-22

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Ralf Rudolf

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/74 ,  H01L21/761 ,  H01L29/10

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is on the semiconductor substrate. A buried semiconductor layer of the second conductivity type is on the first semiconductor layer. A second semiconductor layer of the second conductivity type is on the buried semiconductor layer. A trench extends through each of the second semiconductor layer, the buried semiconductor layer, and the first semiconductor layer, and into the semiconductor substrate. An insulating structure lines walls of the trench. A conductive filling in the trench is electrically coupled to the semiconductor substrate at a bottom of the trench.

公开(公告)号：US10439030B2

公开(公告)日：2019-10-08

申请号：US15646152

申请日：2017-07-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L29/92 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L27/12 ,  H01L29/06

Abstract: A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

公开(公告)号：US20190097042A1

公开(公告)日：2019-03-28

申请号：US16144880

申请日：2018-09-27

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Romain Esteve ,  Roland Rupp

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a semiconductor body of silicon carbide. The trench gate structures include a gate electrode and are spaced apart from one another along a first horizontal direction and extend into a body region with a longitudinal axis parallel to the first horizontal direction. First sections of first pn junctions between the body regions and a drift structure are tilted to the first surface and parallel to the first horizontal direction. Source regions form second pn junctions with the body regions. A gate length of the gate electrode along a second horizontal direction orthogonal to the first horizontal direction is greater than a channel length between the first sections of the first pn junctions and the second pn junctions.

公开(公告)号：US10205016B2

公开(公告)日：2019-02-12

申请号：US15484206

申请日：2017-04-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Detlef Weber ,  Karl-Heinz Gebhardt

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/40 ,  H01L29/10 ,  H01L27/06 ,  H01L27/092

Abstract: A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.

公开(公告)号：US20180286944A1

公开(公告)日：2018-10-04

申请号：US15941637

申请日：2018-03-30

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Karl-Heinz Bach ,  Christian Kampen ,  Dietmar Kotz ,  Andrew Christopher Graeme Wood ,  Markus Zundel

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/10 ,  H01L21/266 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0619 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor body having a semiconductor substrate of a first conductivity type and a semiconductor layer of the first conductivity type on the substrate. A trench structure extends into the semiconductor body from a first surface and includes a gate electrode and at least one field electrode arranged between the gate electrode and a bottom side of the trench structure. A body region adjoins the trench structure and laterally extends from a transistor cell area into an edge termination area. A pn junction is between the body region and semiconductor layer. A doping concentration of at least one of the body region and semiconductor layer is lowered at a lateral end of the pn junction in the edge termination area compared to a doping concentration of the at least one of the body region and semiconductor layer at the pn junction in the transistor cell area.

公开(公告)号：US10002959B2

公开(公告)日：2018-06-19

申请号：US15429282

申请日：2017-02-10

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L23/528 ,  H01L29/66 ,  H01L23/34

CPC classification number: H01L29/7804 ,  H01L23/34 ,  H01L23/5283 ,  H01L27/0705 ,  H01L27/0727 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/42304 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/732 ,  H01L29/7813 ,  H01L29/7826 ,  H01L29/7835 ,  H01L29/8613

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a source contact, the source contact including a first and second source contact portion, and a gate electrode in a gate trench in the first main surface adjacent to a body region. The body region and a drift zone are disposed along a first direction parallel to the first main surface between the source region and a drain region. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region, the first source contact portion further including a portion of the semiconductor substrate between the source conductive material and the second source contact portion. The semiconductor device further includes a temperature sensor in the semiconductor substrate.

公开(公告)号：US09953968B2

公开(公告)日：2018-04-24

申请号：US14628823

申请日：2015-02-23

Applicant: Infineon Technologies AG

Inventor： Yiqun Cao ,  Ulrich Glaser ,  Magnus-Maria Hell ,  Julien Lebon ,  Michael Mayerhofer ,  Andreas Meiser ,  Matthias Stecher ,  Joost Willemen

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0292 ,  H02H9/046

Abstract: An integrated circuit having an ESD protection structure is described. One embodiment includes a circuit section interconnected with a first terminal and with a second terminal and being operable at voltage differences between the first terminal and second terminal of greater than +10 V and less than −10 V. The integrated circuit additionally includes an ESD protection structure operable to protect the circuit section against electrostatic discharge between the first terminal and the second terminal. The ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than −10 V without triggering. The ESD protection structure is electrically and optically coupled to a photon source such that photons emitted by the photon source upon ESD pulse loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons.

公开(公告)号：US20180097074A1

公开(公告)日：2018-04-05

申请号：US15833576

申请日：2017-12-06

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Oliver Haeberlen

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: A method of manufacturing a semiconductor device is providing, which includes forming a trench in a semiconductor substrate, forming an oxide layer over sidewalls and over a bottom side of the trench, performing an ion implantation process, forming a cover layer, and patterning the covering layer, thereby forming an uncovered area and a covered area of the oxide layer, respectively. The method further includes performing an isotropic etching process thereby removing portions of the uncovered area of the oxide layer and removing a part of a surface portion of the covered area adjacent to the uncovered portions, and removing remaining portions of the covering layer.

公开(公告)号：US09893178B2

公开(公告)日：2018-02-13

申请号：US15187889

申请日：2016-06-21

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Franz Hirler

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/108 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/808 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H01L29/8083

Abstract: A semiconductor device includes a transistor formed in a semiconductor substrate having a main surface. The transistor includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, a gate trench adjacent to a first sidewall of the channel region, a gate conductive material disposed in the gate trench, the gate conductive material being connected to a gate terminal, and a channel separation trench adjacent to a second sidewall of the channel region. The second sidewall faces the first sidewall via the channel region. The channel separation trench is filled with an insulating separation trench filling consisting of an insulating material in direct contact with the channel region. The source region and the drain region are disposed along a first direction. The first direction is parallel to the main surface.