公开(公告)号：US10205016B2

公开(公告)日：2019-02-12

申请号：US15484206

申请日：2017-04-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Detlef Weber ,  Karl-Heinz Gebhardt

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/40 ,  H01L29/10 ,  H01L27/06 ,  H01L27/092

Abstract: A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.

公开(公告)号：US20170301791A1

公开(公告)日：2017-10-19

申请号：US15484206

申请日：2017-04-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Detlef Weber ,  Karl-Heinz Gebhardt

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L21/26586 ,  H01L21/823418 ,  H01L27/0623 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7835

Abstract: A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.