公开(公告)号：WO1981000497A1

公开(公告)日：1981-02-19

申请号：PCT/US1980001003

申请日：1980-07-18

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  MARIK C

IPC: H04H05/00

CPC classification number: H04H20/49 ,  G06G7/22

Abstract: A function generator as for use in a system of compatible quadrature AM stereo approximates the tangent function curve, allowing for the provision of essentially undistorted intelligence signals, A form of differential amplifier, including additional multiple threshold transistor circuits (Q2, Q2, Q3, Q4, Q5, Q6) with common collectors and common bases, has at its input terminals a signal related to an angle of modulation and provides an output signal approaching a signal related to the tangent of the angle of modulation, the accuracy of the approximation depending on the number of circuits included. The function generator has the capability of providing other similar functions and of use in other applications. As used for AM stereo decoding, a tangent function output is derived from the phase modulation components of the stereo derived from the phase modulation components of the stereo signal and, when multiplied by the amplitude modulated signal, the stereo difference signal can be derived.

公开(公告)号：WO1981000494A1

公开(公告)日：1981-02-19

申请号：PCT/US1980000959

申请日：1980-07-21

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  MCALLISTER D ,  PFIESTER J

IPC: G11C08/00

CPC classification number: G11C8/10 ,  G11C11/4087 ,  H03K19/09441 ,  H03K19/096

Abstract: A decoder circuit suitable for integrated circuit implementation using IGFET processing which may be implemented in a highly dense structure. The decoder output lines (54', 56') are grouped in pairs and at least one of the output lines in each pair is discharged as determined by a bit in the input address. A plurality of IGFET devices under the control of the remaining input address bits selectively couple together the two output lines in each pair such that both output lines can then become discharged. Series-coupled pairs of IGFET devices (38, 40) are used in place of a single IGFET device (30) in order to reduce the chip area required to implement the decoder structure.

公开(公告)号：WO1981000472A1

公开(公告)日：1981-02-19

申请号：PCT/US1980001005

申请日：1980-08-07

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  SMITH P

IPC: G06F07/50

CPC classification number: G06F7/5055 ,  G06F9/321

Abstract: An increment/ decrement circuit which is implemented using CMOS transistors. The circuit has a minimum of interconnect lines to an adjoining increment/ decrement circuit and also uses a reduced number of transistors. The increment/ decrement circuit has a carry/ borrow generator (17, 18, 19 and 21) and has an increment/ decrement output portion (31, 32).The carry/ borrow generator uses only three transistors (17, 18, 19) plus an inverter (21) and two coupling transistors (13, 14). The increment/ decrement output portion uses only six transistors (22, 23, 24, 25, 28 and 29).

公开(公告)号：WO1981000179A1

公开(公告)日：1981-01-22

申请号：PCT/US1980000827

申请日：1980-06-30

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  GUILLIEN M

IPC: H03F03/26

CPC classification number: H03F3/3081

Abstract: A circuit for converting an asymmetrical input signal applied to a single ended input terminal (30) of the circuit to a symmetrical output voltage appearing across balanced differential outputs (16, 18 respectively). The circuit includes first and second operational amplifiers (12, 14 respectively), the outputs of which are the outputs of the circuit. The noninverting inputs of the two amplifiers being coupled to a reference voltage (VR). The inverting input of the first amplifier (12) being adapted to receive the input signal and further being coupled through a first resistor (32) to the output thereof. The inverting input of the second amplifier (14) being coupled both to the output thereof and the output of the first amplifier (12) through respective second (34) and third resistors (36).

公开(公告)号：WO1980002861A1

公开(公告)日：1980-12-24

申请号：PCT/US1980000703

申请日：1980-06-02

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  WRATHALL R

IPC: F02P05/04

CPC classification number: F02P5/15 ,  F02P3/0456 ,  Y02T10/46

Abstract: Ignition control system (10). Crankshaft advance (15, 16) and reference (17, 18) sensors are utilized to determine positions of maximum and minimum possible spark ignition advance. for each maximum advance pulse (t u a main counter (41) starts sequentially counting clock pulses (C u) wherein the maximum count obtained by the counter (41) is related to engine crankshaft speed. The count of the main counter (41) is utilized by a dwell circuit (121) to determine the time (t u) prior to the maximum advance pulse (t- u) at which spark coil excitation should occur. The main counter count also determines several inputs to a read-only-memory (ROM) circuit (48) whose output controls a rate multiplier (53) which receives input clock signals (C u) and provides selective frequency division for these clock signals in accordance with the ROM output. The output of the rate multiplier is coupled to an accumulator means (80, 81, 82) which provides an accumulated count which is utilized to determine spark occurrence. Pulse width modulation circuitry (56) receives an analog signal related to the amount of sensed engine vacuum pressure and produces a corresponding periodic digital two-state signal which has a duty cycle related to the magnitude of the analog vacuum signal. This signal is coupled as an input to the ROM (53) which controls the rate multiplier. In this manner the accumulator count is made to depend upon the magnitude of the analog vacuum signal.

Abstract translation: 点火控制系统（10）。 曲轴前进（15,16）和参考（17,18）传感器用于确定最大和最小可能的火花点火提前的位置。 对于每个最大提前脉冲（t u，主计数器（41）开始顺序地计数由计数器（41）获得的最大计数与发动机曲轴速度相关的时钟脉冲（C u）。 主计数器（41）的计数由驻留电路（121）利用以确定在应该发生火花线圈激励的最大提前脉冲（t-uA u）之前的时间（t U） 。 主计数器还确定对只读存储器（ROM）电路（48）的多个输入，其输出控制接收输入时钟信号（C u）的速率倍增器（53）并为这些输入时钟信号提供选择性分频 时钟信号按照ROM输出。 速率倍增器的输出耦合到累加器装置（80,81,82），其提供用于确定火花发生的累积计数。 脉冲宽度调制电路（56）接收与感测到的发动机真空压力的量相关的模拟信号，并产生具有与模拟真空信号幅度有关的占空比的对应的周期性数字双态信号。 该信号作为输入耦合到控制速率倍增器的ROM（53）。 以这种方式，累加器计数取决于模拟真空信号的大小。