公开(公告)号：WO1981000473A1

公开(公告)日：1981-02-19

申请号：PCT/US1980001006

申请日：1980-08-07

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  SMITH P ,  RAGHUNATHAN K

IPC: G06F09/06

CPC classification number: G06F9/321 ,  G06F15/7832

Abstract: A CMOS microprocessor having a plurality of registers wherein the registers contain RAM type storage cells resulting in compact, fully static register. In most cases the registers are connected to two buses. A 5 bit temporary register (34) and an 8 bit program counter (23) are each connected to three buses. An incrementer (21), (38) can provide an increment or decrement function but cannot be used to store functions. A bit code generator (44) is connected to a data bus (12) thereby allowing any one selected data bit carried by the data bus to be modified. A 5 bit high order program counter (33) is capable of directly transferring its contents to the 5 bit temporary register (34). An 8 bit low order incrementer (21) is capable of incrementing three different registers which are an address storage register (22), a program counter (23), and a stack pointer (24). A 5 bit high order incrementer (38) is also capable of incrementing three registers which are an address storage register (32), a program counter (33), and a temporary register (34). An ALU (11) has a first and a second input, which, because of the bus structure used, can both receive data simultaneously.

公开(公告)号：WO1981000472A1

公开(公告)日：1981-02-19

申请号：PCT/US1980001005

申请日：1980-08-07

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  SMITH P

IPC: G06F07/50

CPC classification number: G06F7/5055 ,  G06F9/321

Abstract: An increment/ decrement circuit which is implemented using CMOS transistors. The circuit has a minimum of interconnect lines to an adjoining increment/ decrement circuit and also uses a reduced number of transistors. The increment/ decrement circuit has a carry/ borrow generator (17, 18, 19 and 21) and has an increment/ decrement output portion (31, 32).The carry/ borrow generator uses only three transistors (17, 18, 19) plus an inverter (21) and two coupling transistors (13, 14). The increment/ decrement output portion uses only six transistors (22, 23, 24, 25, 28 and 29).

公开(公告)号：WO1982000907A1

公开(公告)日：1982-03-18

申请号：PCT/US1981000951

申请日：1981-07-13

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  SMITH P

IPC: G06F07/48

CPC classification number: G06F7/575

Abstract: Une unite arithmetique et logique statique a CMOS est capable de selectionner un operande a partir d'une pluralite d'entrees (DBn, (Alpha)DBn, (Alpha)DBn+1, (Alpha)DBn-1) et peut executer plusieurs operations arithmetiques et logiques en plus des operations de decalage vers la gauche et vers la droite. L'unite arithmetique et logique utilise des portes OR exclusif (43-46, 53-54) possedant un nombre minimal de transistors. En outre, on utilise davantage de transistors a canal N que de transistors a canal P ce qui permet d'obtenir une taille reduite et une vitesse de fonctionnement accrue. L'unite arithmetique et logique possede en outre une cellule de memoire a acces selectif (61, 62) servant de stockage temporaire et pouvant commander le bus de donnees de l'unite arithmetique et logique (14, 15).