公开(公告)号：US20220416154A1

公开(公告)日：2022-12-29

申请号：US17902895

申请日：2022-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H01L43/02 ,  H01L21/768 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

公开(公告)号：US11469368B2

公开(公告)日：2022-10-11

申请号：US16207206

申请日：2018-12-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H01L43/02 ,  H01L21/768 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; and removing the sacrificial layer.

公开(公告)号：US20200227550A1

公开(公告)日：2020-07-16

申请号：US16828903

申请日：2020-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/417 ,  H01L27/092 ,  H01L29/778 ,  H01L29/66 ,  H01L27/04 ,  H01L29/24

Abstract: A semiconductor device includes a substrate, a first dielectric layer on the substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, an ILD layer overlying the trench, an nFET disposed over the trench, and a pFET disposed over the trench and spaced apart from the nFET.

公开(公告)号：US10529837B1

公开(公告)日：2020-01-07

申请号：US16120296

申请日：2018-09-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Meng-Chi Chiang ,  Yen-Chih Lin

IPC: H01L29/737 ,  H01L29/739 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/10

Abstract: A bipolar junction transistor (BJT) includes an emitter region, abase region on one side of the emitter region, and a collector region on the other side of the base region. The emitter region includes first fins extending along a first direction, a first metal gate extending across the first fins along a second direction, a second metal gate in parallel with the first metal gate, and an emitter contact plug on the first fins between the first metal gate and the second metal gate. The base region includes second fins extending along the first direction, the first metal gate and the second metal gate extending across the second fins along the second direction, and a base contact plug on the second fins between the first metal gate and the second metal gate. The emitter contact plug is aligned with the base contact plug.

公开(公告)号：US20190341544A1

公开(公告)日：2019-11-07

申请号：US15996524

申请日：2018-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yu-Ping Wang

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

公开(公告)号：US10446745B1

公开(公告)日：2019-10-15

申请号：US16004446

申请日：2018-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Kun-Ju Li

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L27/12

Abstract: A method of manufacturing a magnetoresistive random access memory cell includes the following steps. A first dielectric layer including a first metal line therein is formed on a substrate. A patterned second dielectric layer is formed over the first dielectric layer, wherein the patterned second dielectric layer includes a recess exposing the first metal line. A barrier layer conformally covers the recess and the patterned second dielectric layer. A metal fills up the recess and on the barrier layer. The metal is planarized until the barrier layer being exposed by serving the barrier layer as a stop layer. A magnetic tunneling junction and a top electrode over the metal are formed, thereby a magnetoresistive random access memory cell being formed.

公开(公告)号：US10403758B2

公开(公告)日：2019-09-03

申请号：US16140551

申请日：2018-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423

Abstract: A vertical MOS transistor includes a substrate having therein a first source/drain region and a first ILD layer. A nanowire is disposed in the first ILD layer. A lower end of the nanowire is in direct contact with the first source/drain region, and an upper end of the nanowire is coupled with a second source/drain region. The second source/drain region includes a conductive layer. A gate electrode is disposed in the first ILD layer. The gate electrode surrounds the nanowire. A contact hole is disposed in the first ILD layer. The contact hole exposes a portion of the first source/drain region. A contact plug is disposed in the contact hole. A second ILD layer covers the first ILD layer.

公开(公告)号：US10276633B1

公开(公告)日：2019-04-30

申请号：US15936377

申请日：2018-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L23/522 ,  H01L43/02 ,  H01L23/528 ,  H01L43/08 ,  H01L43/12 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, first plug, a magnetoresistive random access memory (MRAM) structure, a spacer layer, a seal layer and a first conductive pattern. The substrate has a first region and a second region, and the first plug is disposed on a dielectric layer disposed on the substrate, within the first region. The MRAM structure is disposed in the dielectric layer and electrically connected to the first plug. The spacer layer is disposed both within the first region and the second region, to cover the MRAM structure. The seal layer is disposed on the MRAM structure and the first plug, only within the first region. The first conductive pattern penetrates through the seal layer to electrically connect the MRAM structure.

公开(公告)号：US10062577B1

公开(公告)日：2018-08-28

申请号：US15647232

申请日：2017-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/20 ,  H01L29/16 ,  H01L21/762 ,  H01L21/02 ,  H01L21/308

Abstract: A method of fabricating III-V fin structures includes providing numerous fins. Then, a group III-V material layer is formed to encapsulate an upper portion of each of the fins. Later, part of the group III-V material layer is removed to expose an end of each of the fins, and divides the group III-V material layer into numerous U-shaped structures. Next, a first part of each of the fins and the entire silicon oxide layer are removed. Finally, part of each of the U-shaped structures is removed to segment each of the U-shaped structures into two III-V fin structures.

公开(公告)号：US10026726B2

公开(公告)日：2018-07-17

申请号：US15604685

申请日：2017-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L21/8238 ,  H01L21/768 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L27/02

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.