公开(公告)号：JP2004214793A

公开(公告)日：2004-07-29

申请号：JP2002379692

申请日：2002-12-27

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： NORO MASAO

IPC: H03F1/02 ,  H03F1/52 ,  H03F3/183 ,  H03F3/217 ,  H03F3/30

CPC classification number: H03F3/217 ,  H03F1/0205 ,  H03F1/523 ,  H03F3/3066 ,  H03F2200/465

Abstract: PROBLEM TO BE SOLVED: To make a maximum output constant independently of the magnitude of the impedance of a load.
SOLUTION: A power amplifier 3 amplifies an input signal amplified by an input amplifier 1 via a voltage limiter circuit 2 and a speaker 6 is driven by the amplified signal. A current detection amplifier 5 detects a voltage across a resistor 4 that is proportional to an output current flowing through the speaker 6. The voltage limiter circuit 2 controls the amplitude of the signal to be inputted to the power amplifier 3 in response to the detected current. Thus, the maximum output power can be controlled to be constant independently of the impedance of the speaker 6. Further, an instantaneous output current also controls the voltage limiter circuit 2 so as to be able to independently control a continuous maximum output value and an instantaneous maximum output value.
COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：使负载的阻抗的大小独立于最大输出。 解决方案：功率放大器3经由限压器电路2放大由输入放大器1放大的输入信号，扬声器6由放大信号驱动。 电流检测放大器5检测电阻器4两端的电压，其与流过扬声器6的输出电流成比例。电压限制器电路2响应于检测到的电流而控制要输入到功率放大器3的信号的幅度 。 因此，可以独立于扬声器6的阻抗将最大输出功率控制为恒定。此外，瞬时输出电流还控制限压器电路2，以便能够独立地控制连续的最大输出值和瞬时 最大输出值。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2004064132A

公开(公告)日：2004-02-26

申请号：JP2002215697

申请日：2002-07-24

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TSUJI NOBUAKI ,  NORO MASAO ,  MITSUOKA KUNIHIKO

IPC: H03F3/45

CPC classification number: H03F3/45188

Abstract: PROBLEM TO BE SOLVED: To provide an operational amplifier which avoids the lowering an S/N ratio while coping with a high power voltage.
SOLUTION: High withstand voltage type PMOS transistors MP4, MP5 with their gates biased at specified voltages are interposingly put on a current line between PMOS transistors MP1, MP2 for the input of a differential amplifier stage and a negative potential power source VN. Resistance elements R1, R2 forming a load circuit are interposingly put on current lines between drains of the high withstand voltage PMOS transistors and the power source VN. This limits the drain voltages of the input PMOS transistors MP1, MP2 to a lower limit value of a specified voltage added with a gate threshold voltage, and hence, if the input PMOS transistors MP1, MP2 are usual withstand voltage types, a voltage applied between electrodes of the usual withstand voltage type MOS transistors MP1, MP2 does not exceed their withstanding voltages.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003338060A

公开(公告)日：2003-11-28

申请号：JP2002146601

申请日：2002-05-21

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN ,  NORO MASAO

IPC: G11B7/09

Abstract: PROBLEM TO BE SOLVED: To provide a tracking servo circuit, in which the comparative accuracy of laser beams for the follow-up detection is improved and the tracking servo for reading data is performed at a high speed by effectively removing the component of a superimposing offset voltage VOFF from a detected signal OUT.
SOLUTION: This servo circuit for an optical pickup, which makes the laser beams exactly converge on a pit of the optical disk, has a feature that a VCA.10 for amplifying a reflected signal IN based on the reflection of the laser beams in accordance with the voltage of a trigger signal FB, a VCA.50 for operating the amplification based on the trigger signal FB while being constituted similarly to the VCA.10, and a differential amplifier 54 for outputting the voltage of the difference between an amplified voltage V outputted by the VCA.10 and an amplified voltage VOFFD' outputted by the VCA.50, as a detection signal OUT of the laser beams, are furnished therein.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种跟踪伺服电路，其中提高用于跟踪检测的激光束的比较精度，并且通过有效地去除部件的分量来高速执行用于读取数据的跟踪伺服 来自检测信号OUT的叠加偏移电压VOFF。 解决方案：使激光束精确地会聚在光盘的凹坑上的用于光学拾取器的该伺服电路具有以下特征：用于根据激光束的反射放大反射信号IN的VCA.10 根据触发信号FB的电压，基于触发信号FB进行放大的VCA.50类似于VCA.10构成的VCA.50以及用于输出放大后的差分电压的差分放大器54 由VCA.10输出的电压V和由VCA.50输出的放大电压VOFFD'作为激光束的检测信号OUT。 版权所有（C）2004，JPO

公开(公告)号：JP2003287554A

公开(公告)日：2003-10-10

申请号：JP2002089329

申请日：2002-03-27

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TSUJI NOBUAKI ,  NORO MASAO ,  MITSUOKA KUNIHIKO ,  SEKIMOTO YASUHIKO

IPC: G01R19/165 ,  G05F1/10 ,  H03F3/217

Abstract: PROBLEM TO BE SOLVED: To provide a supply voltage detection circuit for stably detecting a plurality of supply voltages (multiple power supplies) where the supply voltages differ one another.
SOLUTION: A first power supply system is divided by a PMOS transistor MP1 and a resistor R1, and the voltage of the power supply is reflected on a signal appearing at a connection node N3. Additionally, a second power supply system is divided by resistors R2 and R3, and a signal level appearing at a connection node N4 is determined according to whether the gate threshold voltage of a PMOS transistor MP2 is exceeded or not. Further, a third power supply system is divided by PMOS transistors MHP1, MHP2, and a resistor R9, and the supply voltage is reflected on a signal appearing at a connection node N7. The signals appearing at the connection nodes are given to the gates of NMOS transistors MHN1-MHN3, thus generating a detection signal DETECT.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供用于稳定地检测电源电压彼此不同的多个电源电压（多个电源）的电源电压检测电路。 解决方案：第一电源系统由PMOS晶体管MP1和电阻器R1分压，并且电源的电压被反映在出现在连接节点N3处的信号上。 此外，第二电源系统由电阻器R2和R3分压，并且根据PMOS晶体管MP2的栅极阈值电压是否超过来确定出现在连接节点N4处的信号电平。 此外，第三电源系统由PMOS晶体管MHP1，MHP2和电阻器R9分压，并且电源电压反映在出现在连接节点N7处的信号上。 出现在连接节点处的信号被提供给NMOS晶体管MHN1-MHN3的栅极，从而产生检测信号DETECT。 版权所有（C）2004，JPO

公开(公告)号：JP2003115730A

公开(公告)日：2003-04-18

申请号：JP2002182823

申请日：2002-06-24

Applicant: YAMAHA CORP

Inventor： TSUJI NOBUAKI ,  NORO MASAO

IPC: H03K7/08 ,  H03F3/217 ,  H03F3/45

Abstract: PROBLEM TO BE SOLVED: To enable stable negative feedback in a power amplifier circuit employing a PWM circuit by reducing the phase rotation in the circuit. SOLUTION: The PWM circuit 10 comprises a comparator 11 having hysteresis characteristics applied with positive feedback and an integrator 20. In the circuit 10, an input signal from a signal source 16 which is inputted via an amplifier 15 is compared with an integrated output by the comparator 11, thereby outputting a PWM signal having a leading phase characteristic which is obtained by differentiating an input signal. This PWM signal is amplified in a switching circuit 21, is applied to a speaker 27 via an LC filter 26, and is negatively fed back to an input side via a resistor 28. The PWM signal which is leading in phase passes through the filter 26, thereby reducing the phase rotation of the output to enable an stable negative feedback operation.

公开(公告)号：JP2003101357A

公开(公告)日：2003-04-04

申请号：JP2001289824

申请日：2001-09-21

Applicant: YAMAHA CORP

Inventor： NORO MASAO ,  SEKIMOTO YASUHIKO

IPC: H03M1/08 ,  H03F1/34 ,  H03F3/217 ,  H03M1/36 ,  H03M1/82

Abstract: PROBLEM TO BE SOLVED: To provide a D-class amplifier improved in S/N and reduced in distortion factor. SOLUTION: The amplifier is constituted by an integrating circuit 1 for integrating an input signal, a flash A/D convertor 2 for performing A/D conversion on an output signal of the integrating circuit 1, a waveform conversion circuit 3 for generating a PWM signal with a pulse width corresponding to a digital value outputted from the flash A/D converter, and a pair of MOS transistors 5 and 6 connected between a first power supply and a second power supply. The amplifier has a switching circuit in which a node P of the pair of MOS transistors 5 and 6 is connected to a speaker 51 serving as a load, a driving circuit 4 for driving the pair of MOS transistors 5 and 6 in response to a PWM signal outputted from the waveform conversion circuit 3, and a feedback resistor RNF serving as a feedback circuit which is connected to the node P and the input side of the integrating circuit 1 and performs negative feedback on an output signal of the amplifier, the signal being supplied to the speaker 51.

公开(公告)号：JP2003060449A

公开(公告)日：2003-02-28

申请号：JP2001245182

申请日：2001-08-13

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： NORO MASAO

IPC: G01R19/00 ,  G01R19/165 ,  H02M1/00 ,  H02M7/5387 ,  H03F1/30 ,  H03F1/52 ,  H03F3/217 ,  H03K17/08

CPC classification number: H03F1/523 ,  H03F3/2171

Abstract: PROBLEM TO BE SOLVED: To obtain high current detecting accuracy, without bringing about new power loss to detect a current.
SOLUTION: A current detector circuit comprises sample hod capacitors C1, C2 for holding a voltage between switching transistors P1 and N1, when the transistors P1, N1 are on, analog switches 31, 32 connected between the transistors P1 and N1 via the capacitors C1, C2, a control circuit 30 for controlling, so that the switches 31, 32 are turned on synchronously with a timing in which the transistors P1, N1 are turned on, and buffer amplifiers 33, 34 for outputting a voltage between both terminals of the transistors P1, N1 which are held at the capacitors C1, C2 and are on, as a detection voltage.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：为了获得高电流检测精度，不会引起新的功率损耗来检测电流。 解决方案：当晶体管P1，N1导通时，电流检测器电路包括用于保持开关晶体管P1和N1之间的电压的采样霍尔电容器C1，C2，经由电容器C1连接在晶体管P1和N1之间的模拟开关31,32， C2，用于控制的开关31,32与晶体管P1，N1导通的定时同步导通的控制电路30以及用于输出晶体管的两端的电压的缓冲放大器33,34 保持在电容器C1，C2并导通的P1，N1作为检测电压。

公开(公告)号：JP2001292065A

公开(公告)日：2001-10-19

申请号：JP2000311169

申请日：2000-10-11

Applicant: YAMAHA CORP

Inventor： NORO MASAO ,  TAKAHASHI KUNIHITO ,  YASUI SHOJI

IPC: H03M1/66 ,  H03M1/68 ,  H03M1/76 ,  H03M1/78 ,  H03M1/80

Abstract: PROBLEM TO BE SOLVED: To provide a digital/analog converter with high accuracy that is capable of multi-bits processing and configured with CMOS transistors(TRs). SOLUTION: A switch matrix circuit 1 consists of a resistor string 5 comprising resistors in series connection, switches S0a-S8a, S0b-S8b, amplifiers 16, 17 and resistors 6, 7 connected like a matrix state. Each switch is on/off- controlled by a signal resulting from decoding high-order 4-bits of data to be converted and a voltage corresponding to the high-order 4-bits of the data to be converted is obtained as an output of the amplifiers 16, 17 thereby. A low-order bit conversion circuit 2 is a circuit conducting digital/analog conversion adopting conventional resistance weighting and converts low-order 4-bits of the data to be converted into an analog voltage. An operational amplifier 3 synthesizes the outputs of the circuits 1, 2 to obtain an analog conversion output.

公开(公告)号：JP2001156639A

公开(公告)日：2001-06-08

申请号：JP34148199

申请日：1999-11-30

Applicant: YAMAHA CORP

Inventor： NORO MASAO ,  TODA AKIHIKO

IPC: H03M1/68 ,  H03M1/06 ,  H03M1/72 ,  H03M1/74 ,  H03M1/76

Abstract: PROBLEM TO BE SOLVED: To provide a digital/analog converter that can prevent the accuracy from being deteriorated due to dispersion in characteristics of resistors and transistors(TRs). SOLUTION: High-order eight bits in 12-bit converted data are applied to a decoder 21 and low-order four-bits are fed to a current summing circuit 22. A decoder 21 selects any of FET F0-F255 based on the high-order eight bits to apply any of voltages divided by a series circuit consisting of resistors t0-t255 to an operational amplifier 40. Switches 30-33 of the current summing circuit 22 are switch-controlled by the low-order four-bits and FETs 35-38 are on/off- controlled by the switches. Then the currents of the conductive FETs are composited and the resulting current flows to a resistor ra. The operational amplifier 40 composites both the voltages and provides an output. The FET 24 and the FETs 35-38 configure current mirror circuits so as to eliminate the effect of dispersion in the resistance.

公开(公告)号：JP2001121079A

公开(公告)日：2001-05-08

申请号：JP30175299

申请日：1999-10-22

Applicant: YAMAHA CORP

Inventor： NORO MASAO ,  TANAKA TAKAHIRO ,  TOBA NOBUKAZU ,  YAMAKI KIYOSHI

IPC: H04R1/00 ,  B06B1/02 ,  B06B1/04 ,  G08B6/00 ,  H04M1/00

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus for driving a vibration source which can give a joy without causing a feeling of something wrong when an incoming of a call is announced by generating sound and vibration simultaneously. SOLUTION: An apparatus has a sound source 10 for producing a sound signal, a DC motor 24 as a vibration source for generating vibration, a low-pass filter(LPF) 16 as a signal extracting means extracting low area components from the sound signal output from the sound source 10, a detection circuit 18 for detecting the detection output of the circuit 18, a rectification circuit 20 for rectifying the detection output of the circuit 18, an amplifier 22 for driving the vibration source on the basis of the sound signal of the low area components extracted by the low-pass filter 16.