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公开(公告)号：WO0141310A9
公开(公告)日：2002-10-03
申请号：PCT/JP0008248
申请日：2000-11-22
Applicant: YAMAHA CORP , NORO MASAO , TODA AKIHIKO
Inventor： NORO MASAO , TODA AKIHIKO
CPC classification number: H03M1/0619 , H03M1/687 , H03M1/745 , H03M1/765
Abstract: A decoder (21) selects one of FETs (F0 to F255) based on higher bits, and applies one of the voltages divided by a series circuit of resistors (r0 to r255) to an operational amplifier (40). Switches (30 to 33) of a current adder circuit (22) are switched by lower bits to turn on and off FETs (35 to 38). The currents flowing through the conducting FETs are combined, and the resulting current flows to a resistor (ra), across which a voltage appears. The operational amplifier (40) combines two input voltages to produce an output. A FET (24) and FETs (35 to 38) form a current mirror circuit, which prevents the voltage width of each LSB of higher and lower bits from changing if the current (i) through the series circuit of resistors (r0 to r255) changes because of irregularities of manufacturing processes.
Abstract translation: 解码器（21）基于较高位选择FET（F0〜F255）中的一个，并且将由电阻（r0〜r255）的串联电路分压的电压中的一个施加到运算放大器（40）。 电流加法器电路（22）的开关（30〜33）由低位开关导通和截止FET（35〜38）。 流过导通FET的电流被组合，并且所得到的电流流向电阻（ra），电阻出现在电阻（ra）上。 运算放大器（40）组合两个输入电压以产生输出。 FET（24）和FET（35〜38）形成电流镜电路，如果电流（i）通过电阻（r0〜r255）的串联电路，则阻止高位和低位的每个LSB的电压宽度改变， 由于制造过程的不规则而改变。
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公开(公告)号：ES2352724T3
公开(公告)日：2011-02-22
申请号：ES04022452
申请日：2000-10-23
Applicant: YAMAHA CORP
Inventor： NORO MASAO , TANAKA TAKAHIRO , TOBA NOBUKAZU , YAMAKI KIYOSHI
Abstract: Un dispositivo de excitación de fuente de vibraciones que comprende: una fuente (10) de sonido para generar señales de tono musical; un secuenciador (40) para excitar y controlar la fuente de sonido (10) basándose en datos de secuencia, concretamente datos musicales; un medio (22) de excitación para excitar una fuente (24, 26) de vibración; y un medio de conmutación (42) para encender o apagar una señal a suministrar al medio de excitación (22) bajo el control del secuenciador (40), en el cual el secuenciador (40) está adaptado para controlar el medio de conmutación (42) basándose en datos de temporización incluidos en los datos de secuencia.
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公开(公告)号：AU1549201A
公开(公告)日：2001-06-12
申请号：AU1549201
申请日：2000-11-22
Applicant: YAMAHA CORP
Inventor： TODA AKIHIKO , MAEJIMA TOSHIO , NORO MASAO
Abstract: A resistor string D/A converter for converting input data to multiple-bit data without increasing the number of resistors. The higher four bits of input data to be converted are supplied to a decoder (1) while the lower four bits are applied to a decoder (3) through an inverter (2). The decoder (1) decodes the higher four bits and turns on one of FETs (F0-F15) based on the decoded result. As a result, one of the voltages at the nodes between series resistors (r0-r15) is selected and applied to an operational amplifier (6). Similarly, the voltage corresponding to the lower four bits of the data is applied to an operational amplifier (7). The output from the operational amplifier (7) is divided by 16 through resistors (ra, rb), and the resulting voltage is combined with the voltage applied to the operational amplifier (6) to produce an analog voltage corresponding to the input data.
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公开(公告)号：AU1549101A
公开(公告)日：2001-06-12
申请号：AU1549101
申请日：2000-11-22
Applicant: YAMAHA CORP
Inventor： NORO MASAO , TODA AKIHIKO
Abstract: There is provided a D/A converter that is free from a variation in the voltage width of 1 LSB between more significant bits and less significant bits of data for conversion due to variations in characteristics of resistors, transistors, etc. to thereby ensure a higher conversion accuracy than the conventional D/A converter. The eight more significant bits of 12-bit data for conversion are applied to a decoder 21, while the four less significant bits of the same are applied to a current addition circuit 22. The decoder 21 selects one of FET's F0 to F255 based on the eight more significant bits to cause one of voltages divided by a series circuit formed by resistors r0 to r255 to be applied to an operational amplifier 40. On the other hand, switches 30 to 33 of the current addition circuit 22 are switched, respectively, by the four less significant bits to turn respective FET's 35 to 38 on and off. As a result, currents flowing through turned-on ones of the FET's 35 to 38 are synthesized to flow through the resistor ra so that a voltage is generated across the resistor ra. The operational amplifier 40 synthesizes the two voltages and then outputs the synthesized voltage. An FET 24 and each of the FET's 35 to 38 form a current mirror circuit, whereby the influence of variations in characteristics of the resistors, etc. is eliminated.
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公开(公告)号：DE68921922T2
公开(公告)日：1995-12-07
申请号：DE68921922
申请日：1989-05-19
Applicant: YAMAHA CORP
Inventor： NORO MASAO
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Patent Agency Ranking
公开(公告)号：EP3145214A4
公开(公告)日：2017-11-08
申请号：EP15792641
申请日：2015-05-14
Applicant: YAMAHA CORP
Inventor： NORO MASAO
CPC classification number: H04R1/24 , H04R7/12 , H04R7/127 , H04R7/18 , H04R7/20 , H04R7/26 , H04R9/025 , H04R9/04 , H04R9/06
Abstract: An electroacoustic transducer with a single speaker unit is provided which has a wide directivity over a wide frequency range from low frequencies to high frequencies. The electroacoustic transducer includes: a diaphragm 1 including a cone portion 11 having a conical shape such as a circular conical surface shape or an oval conical surface shape, and a wing-pair portion 14 having a pair of longitudinal split tubular surfaces 12 arranged next to each other, a valley being formed between a side portion of one of the longitudinal split tubular surfaces 12 and a side portion of the other of the longitudinal split tubular surfaces 12; a converter that performs conversion between vibration of the diaphragm along an axis of the cone portion and an electric signal corresponding to the vibration; and a supporter that supports the diaphragm such that the diaphragm is movable in an axial direction of the cone portion. The small-diameter-side end portion of the cone portion, and a bottom portion of a valley of the wing-pair portion are secured to the converter.
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公开(公告)号：EP1624718A4
公开(公告)日：2009-05-27
申请号：EP04731478
申请日：2004-05-06
Applicant: YAMAHA CORP
Inventor： USUI AKIRA , NORO MASAO
CPC classification number: H04R3/12 , H04R2203/12 , H04R2205/022 , H04S3/00
Abstract: An array speaker system comprising a plurality of speaker units each provided with a weighting means to give it weighting by a weighting factor based on Bessel function. An input signal is supplied to a speaker unit having a negative weighting factor after passed through an all path filter where the phase in the high-frequency band is rotated by 180°. Accordingly, a negative-phase signal is output for a signal in a low-frequency area to thereby prevent the lowering of acoustic radiation characteristics and also prevent acoustic radiation characteristics for a high-frequency-area signal from being formed into beams or comb shapes (COMB).
Abstract translation: 一种阵列扬声器系统，包括多个扬声器单元，每个扬声器单元设置有加权装置，以基于贝塞尔函数的加权因子给予加权。 在通过高频带中的相位旋转180°的全通路滤波器之后，输入信号被提供给具有负加权因子的扬声器单元。 因此，对于低频区域中的信号输出负相信号，从而防止声辐射特性的降低，并且还防止高频区域信号的声辐射特性形成为波束或梳形（ 梳）。
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公开(公告)号：DE60017937T2
公开(公告)日：2006-01-12
申请号：DE60017937
申请日：2000-11-22
Applicant: YAMAHA CORP
Inventor： NORO MASAO , TODA AKIHIKO
Abstract: There is provided a D/A converter that is free from a variation in the voltage width of 1 LSB between more significant bits and less significant bits of data for conversion due to variations in characteristics of resistors, transistors, etc. to thereby ensure a higher conversion accuracy than the conventional D/A converter. The eight more significant bits of 12-bit data for conversion are applied to a decoder 21, while the four less significant bits of the same are applied to a current addition circuit 22. The decoder 21 selects one of FET's F0 to F255 based on the eight more significant bits to cause one of voltages divided by a series circuit formed by resistors r0 to r255 to be applied to an operational amplifier 40. On the other hand, switches 30 to 33 of the current addition circuit 22 are switched, respectively, by the four less significant bits to turn respective FET's 35 to 38 on and off. As a result, currents flowing through turned-on ones of the FET's 35 to 38 are synthesized to flow through the resistor ra so that a voltage is generated across the resistor ra. The operational amplifier 40 synthesizes the two voltages and then outputs the synthesized voltage. An FET 24 and each of the FET's 35 to 38 form a current mirror circuit, whereby the influence of variations in characteristics of the resistors, etc. is eliminated.
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公开(公告)号：HK1070319A1
公开(公告)日：2005-06-17
申请号：HK05103100
申请日：2005-04-12
Applicant: YAMAHA CORP
Inventor： NORO MASAO , TANAKA TAKAHIRO , TOBA NOBUKAZU , YAMAKI KIYOSHI
IPC: B06B20060101 , H04R1/00 , B06B1/02 , B06B1/04 , G08B6/00 , H04M1/00 , H04R20060101
Abstract: A vibration source driving device comprises a sound source 10 for generating musical tone signals, a DC motor 24 as a vibration source for generating vibration, a low-pass filter (LPF) 16 as a signal extraction means for extracting low-frequency components from the musical tone signals output from the sound source 10, a detection circuit 18 for detecting the output signal of the low-pass filter 16, a rectifier circuit 20 for rectifying the detection output of the detection circuit 18, and an amplifier for driving the vibration source based on the low-frequency components of the musical tone signals that are extracted by the low-pass filter 16.
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公开(公告)号：DE60017937D1
公开(公告)日：2005-03-10
申请号：DE60017937
申请日：2000-11-22
Applicant: YAMAHA CORP
Inventor： NORO MASAO , TODA AKIHIKO
Abstract: There is provided a D/A converter that is free from a variation in the voltage width of 1 LSB between more significant bits and less significant bits of data for conversion due to variations in characteristics of resistors, transistors, etc. to thereby ensure a higher conversion accuracy than the conventional D/A converter. The eight more significant bits of 12-bit data for conversion are applied to a decoder 21, while the four less significant bits of the same are applied to a current addition circuit 22. The decoder 21 selects one of FET's F0 to F255 based on the eight more significant bits to cause one of voltages divided by a series circuit formed by resistors r0 to r255 to be applied to an operational amplifier 40. On the other hand, switches 30 to 33 of the current addition circuit 22 are switched, respectively, by the four less significant bits to turn respective FET's 35 to 38 on and off. As a result, currents flowing through turned-on ones of the FET's 35 to 38 are synthesized to flow through the resistor ra so that a voltage is generated across the resistor ra. The operational amplifier 40 synthesizes the two voltages and then outputs the synthesized voltage. An FET 24 and each of the FET's 35 to 38 form a current mirror circuit, whereby the influence of variations in characteristics of the resistors, etc. is eliminated.
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