中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19053 records (took 0.08 seconds)

    METHOD OF ECHO CANCELLATION AND SUBSCRIBER LINE AUDIO PROCESSING CIRCUIT
    141.
    发明专利
    METHOD OF ECHO CANCELLATION AND SUBSCRIBER LINE AUDIO PROCESSING CIRCUIT 失效

    公开(公告)号：JPH01151830A

    公开(公告)日：1989-06-14

    申请号：JP24894188

    申请日：1988-10-01

    Applicant: ADVANCED MICRO DEVICES INC

    Inventor： KANAN PII BAIRABAN ,  POORU MAKURANDO

    IPC: H04B3/23

    Abstract: PURPOSE: To achieve a substantially improved learning curve by updating an adaptive digital filter coefficient corresponding to nonlinear signal algorithm. CONSTITUTION: The utilization of CSD updating algorithm is especially suitable for an adaptive filter 10 and it is because it depends on only the code of the product of Xn and En decided by an exclusive OR function. An error En is equal to input signals dn first and the error En is reduced as the filter 10 is adapted to a specified line state and finally becomes close to a residual limit. When the filter is adapted, residual errors fluctuate near a small value. Thus, in simulated adaptation for utilizing present color noise as input Xn and utilizing the CSD updating algorithm to the coefficient of the filter 10, convergence to the residual limit is obtained within about 5000 repetition.

    METHOD OF INCREASING AND DECREASING DECIMATED DIGITAL FILTER TAP COEFFICIENT
    142.
    发明专利
    METHOD OF INCREASING AND DECREASING DECIMATED DIGITAL FILTER TAP COEFFICIENT 失效

    公开(公告)号：JPS6471210A

    公开(公告)日：1989-03-16

    申请号：JP12039688

    申请日：1988-05-17

    Applicant: ADVANCED MICRO DEVICES INC

    Inventor： KAANAN PII BUAIRABUAN ,  POURU MAKURAUDO

    IPC: H03H21/00 ,  G06F7/49 ,  G06F17/10 ,  H03H17/00 ,  H03H17/02

    Abstract: PURPOSE: To simplify a coefficient update algorithm by limiting the range of respective multiple bit coefficients expressed by binary codes. CONSTITUTION: An 8-tap digital filter 10 is provided with seven pieces of storage, namely, delay units 12, eight multipliers 14 and seven adder unit 16. In order to express the tap coefficient of this filter 10, direct type code signed digit(CSD) coding is adopted. The respective tap coefficients are expressed as a large number of multiple bit coefficient sections arranged from the most significant to the least significant. Since the combined CSD coded values of respective multibit coefficients do not have any direct relation with the decimal values of the coefficients, in this case, the range of respective multibit coefficients is limited. The resulted decimal number is given an increment or decrement corresponding to that range.

    BYTE CUING/DECUING APPARATUS AND METHOD FOR PROCESSING VARIABLE LENGTH DATA WORD/INSTRUCTION BY ONE CLOCK CYCLE
    143.
    发明专利
    BYTE CUING/DECUING APPARATUS AND METHOD FOR PROCESSING VARIABLE LENGTH DATA WORD/INSTRUCTION BY ONE CLOCK CYCLE 失效

    公开(公告)号：JPS6470832A

    公开(公告)日：1989-03-16

    申请号：JP17620688

    申请日：1988-07-13

    Applicant: ADVANCED MICRO DEVICES INC

    Inventor： TEIMOSHII EE ORUSON ,  DAAWARU AJIYUMEERAA

    IPC: G06F9/34 ,  G06F5/16 ,  G06F12/04 ,  G06F12/06

    Abstract: PURPOSE: To buffer a variable length data word in one clock cycle by providing plural FIFOs, an input/output data bus connected thereto, and input/output rotators, and also providing a logic circuit which is supplied with a control signal and a pointer. CONSTITUTION: Four first-in first-out random access memories(FIFO) 0-3 and two rotators 1 and 9 are used. The rotators can process 1-byte to 4-byte variable length data words at a time. The variable length words consisting of 1-4 types can be queued and dequeued by enabling FIFO buffering and FIFO buffering using the painter 7. The bytes are rotated by the rotators, the FIFO buffering is enabled individually, and the control signal indicating the storage place of an active state is generated by a logic circuit.

    SYNCHRONIZER AND METHOD OF SYNCHRONIZING DECODING
    144.
    发明专利
    SYNCHRONIZER AND METHOD OF SYNCHRONIZING DECODING 失效

    公开(公告)号：JPS6436143A

    公开(公告)日：1989-02-07

    申请号：JP17620588

    申请日：1988-07-13

    Applicant: ADVANCED MICRO DEVICES INC

    Inventor： KADEIREESAN ANNAAMAARAI

    IPC: H04L7/00 ,  H04J3/06

    Abstract: PURPOSE: To synchronize a data packet of received 'bytes' by using an adequately delayed readout pointer initialization signal as a byte synchronizing signal. CONSTITUTION: The synchronizing device includes a means 118 for generating an enable signal 160 to be sent to a multi-bit register means 120 in response to a signal generated by delaying the initialized readout pointer signal 140, the detection signal 154 of a comparator means 114 for generating a signal indicating the detection of a delimiter symbol, and a serial synchronized clock signal 80. Then the generation of the enable signal 160 causes a signal generated by a series-parallel register means 116 to be received by the multi-bit register means 120 with the serial synchronized clock signal. Consequently, the bytes of received serial data can be synchronized.

    146.
    发明专利
    失效

    公开(公告)号：JPS6345129B2

    公开(公告)日：1988-09-08

    申请号：JP50184880

    申请日：1980-06-18

    Applicant: ADVANCED MICRO DEVICES INC

    Inventor： AAPUFUERU RATSUSERU JEI ,  ERIKUSOON ANDAASU GUNNAA ,  SUBENSOON RAASU TOMII EDOWAADO

    IPC: H03K3/00 ,  B01D45/08 ,  B01D45/16 ,  F28C1/16 ,  H03H17/00 ,  H03M1/00 ,  H03M3/04 ,  H04B14/04 ,  H03H17/02

    Abstract: An interpolative analog-to-digital converter comprising an integrator (77) for integrating the difference between an input analog signal x(t) and a quantized signal q(t) to develop an integrated signal, a first comparator (78) for sampling the integrated signal at a first sampling frequency and for generating first signals of one data state when the integrated signal is positive and of another data state when the integrated signal is negative, a second comparator (91) for comparing the input signal x(t) to the quantized signal q(t) and for sampling the results of the comparison at the first sampling frequency to develop second signals of one data state when the input signal x(t) is greater than the quantized signal q(t) and of another data state when the input signal x(t) is less than the quantized signal q(t), logic circuitry (93) responsive to the first and second signals and operative to develop a plurality of signals including a sign bit signal, a shift left signal, a shift right signal and a no shift signal, a shift register (98) responsive to the shift left signal, the shift right and the no shift signal and operative to develop a series of multi-bit binary words each having a predetermined number of bits and a magnitude determined by the shift and no shift signals, a digital-to-analog converter (80) responsive to the binary words and the sign bit signal and operative to convert the binary words into the quantized signals q(t), the quantized signals q(t) being positive or negative dependant upon the data state of the sign bit, and a digital signal processor (101) for digitally filtering the series of binary words and for developing binary output signals at a frequency of at least twice the highest signal frequency in the input signal x(t).

Patent Agency Ranking