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    SECURITY FOR ON-CHIP MICROCONTROLLER MEMORY
    141.
    发明申请
    SECURITY FOR ON-CHIP MICROCONTROLLER MEMORY 审中-公开
    片上微控制器存储器的安全性

    公开(公告)号：WO1993010498A1

    公开(公告)日：1993-05-27

    申请号：PCT/US1992009465

    申请日：1992-11-12

    Applicant: MICROCHIP TECHNOLOGY INC.

    Inventor： MICROCHIP TECHNOLOGY INC. ,  BURGHARDT, Martin ,  BERMAN, Eric ,  PADGAONKAR, Ajay ,  ALLEN, Ray

    IPC: G06F12/14

    CPC classification number: G06F12/1433

    Abstract: A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory. The microcontroller operates in any one plurality of operating modes, including a secure microcontroller mode. A plurality of EPROM configuration fuses are mapped into the on-chip EPROM program memory as bits in respective address locations for configuring and protecting the microcontroller program memory from read, verify or write instructions initiated from other than a secure area of the chip. The value of a bit representing one of said fuses reflects the condition of the respective fuse. That condition is observed by reading the value of the respective bit for that fuse stored in the EPROM program memory. The chip security is enabled by configuring the microcontroller in a code protected mode by programming the bits representing the desired fuses in the EPROM program memory to blow or erase each fuse according to the desired configuration.

    Abstract translation: 在半导体芯片上制造的微控制器具有片上EPROM程序存储器。 微控制器以任何多种操作模式工作，包括安全的微控制器模式。 多个EPROM配置熔丝被映射到片上EPROM程序存储器中，作为用于配置和保护微控制器程序存储器的读取，验证或写入从芯片的安全区域以外的指令发起的相应地址位置中的位。 代表所述保险丝之一的位的值反映了各个保险丝的状态。 通过读取存储在EPROM程序存储器中的该熔丝的相应位的值来观察该条件。 通过在EPROM程序存储器中编程表示所需保险丝的位来根据所需的配置对每个保险丝进行烧断或擦除，通过将代码保护模式下的微控制器配置为使能芯片的安全性。

    Processor having Switch Instruction Circuit
    142.
    发明申请
    Processor having Switch Instruction Circuit 有权

    公开(公告)号：US20240394062A1

    公开(公告)日：2024-11-28

    申请号：US18534203

    申请日：2023-12-08

    Applicant: Microchip Technology Inc.

    Inventor： Christopher I. W. NORRIE

    IPC: G06F9/38 ,  G06F9/30

    Abstract: In one implementation a processor has an instruction fetch circuit fetching instructions, the instruction fetch circuit having an input and an output and a decode circuit to decode the fetched instructions, the decode circuit having a first and second input, and an output, wherein the decode circuit first input is coupled to the instruction fetch circuit output receiving the fetched instructions, and an execution circuit executing the decoded fetched instructions, the execution circuit having an input coupled to the decode circuit output to receive the decoded fetched instructions, and a switch instruction circuit (SIC) to detect and execute switch instructions of the fetched instructions, the SIC having an input and an output, wherein the SIC input is coupled to the instruction fetch circuit output to receive the fetched instructions, wherein the SIC output is coupled to the decode circuit second input and the instruction fetch circuit input.

    IC thermal protection
    143.
    发明授权
    IC thermal protection 有权

    公开(公告)号：US12088285B2

    公开(公告)日：2024-09-10

    申请号：US17548988

    申请日：2021-12-13

    Applicant: Microchip Technology Inc.

    Inventor： Tamir Langer ,  Migel Jacubovski

    IPC: H03K17/082 ,  G01K7/01 ,  H02H5/04 ,  H03K17/08

    CPC classification number: H03K17/0822 ,  G01K7/01 ,  H02H5/044 ,  H03K2017/0806

    Abstract: A method provides thermal protection for an IC device that has multiple components. For each component, temperatures are sensed, each of which associated with a different area of the respective component and a respective temperature sense signal is output indicative of the highest sensed temperature of the respective component. For each of the components, the respective temperature sense output signal is sampled to produce a sequence of discrete sampled temperature values. A sequence of differences between a reference temperature value and each of the discrete sample temperatures is integrated over time to compute, for each of the components, a respective integration output. The respective integration output computed for each of the switches is compared to a threshold value. An action related to the thermal protection function is initiated upon the integration output of an affected component exceeding the threshold value.

    Machine learning assisted quality of service (QoS) for solid state drives
    144.
    发明授权
    Machine learning assisted quality of service (QoS) for solid state drives 有权

    公开(公告)号：US11934696B2

    公开(公告)日：2024-03-19

    申请号：US17398091

    申请日：2021-08-10

    Applicant: Microchip Technology Inc.

    Inventor： Lorenzo Zuolo ,  Rino Micheloni

    IPC: G06F3/06 ,  G06N3/08

    CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G06N3/08

    Abstract: A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.

    Logic cell for programmable gate array
    147.
    发明授权
    Logic cell for programmable gate array 有权

    公开(公告)号：US11671099B2

    公开(公告)日：2023-06-06

    申请号：US17529522

    申请日：2021-11-18

    Applicant: Microchip Technology Inc.

    Inventor： Jonathan W. Greene ,  Marcel Derevlean

    IPC: H03K19/17736 ,  H03K19/17728 ,  H03K19/21

    CPC classification number: H03K19/17728 ,  H03K19/17736 ,  H03K19/21

    Abstract: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).

    Memory address protection
    148.
    发明授权
    Memory address protection 有权

    公开(公告)号：US11663076B2

    公开(公告)日：2023-05-30

    申请号：US17825352

    申请日：2022-05-26

    Applicant: Microchip Technology Inc.

    Inventor： Peter John Waldemar Graumann

    IPC: G06F11/10 ,  G06F11/00 ,  H03M13/00

    CPC classification number: G06F11/1048 ,  G06F11/1044

    Abstract: A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.

    Method and apparatus for carrying constant bit rate (CBR) client signals
    149.
    发明公开
    Method and apparatus for carrying constant bit rate (CBR) client signals 审中-公开

    公开(公告)号：US20230163942A1

    公开(公告)日：2023-05-25

    申请号：US17885194

    申请日：2022-08-10

    Applicant: Microchip Technology Inc.

    Inventor： Scott Muma ,  Winston Mok ,  Steven Scott GORSHE

    IPC: H04L7/04 ,  H04J3/06

    CPC classification number: H04L7/04 ,  H04J3/0658 ,  H04L2012/5674

    Abstract: A method and apparatus in which a data stream generated by a previous network node, a cumulative phase offset report (CPOR) and a client rate report (CRR) are received. A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), where IPSD indicates CPSC increment between successive CPSC samples. The data stream is demultiplexed to obtain CBR carrier streams that include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and the PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.

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