Abstract:
A microcontroller (10) fabricated on a semiconductor chip is adapted, when operating, to execute programs (17) and instructions and, in response, to generate control signals to selectively control external apparatus. A clock (15) generates timing signals to control the timing of the microcontroller execution and operation. An on-chip program memory (17) has space available for storing a program to be executed by the microcontroller in sequential steps in successive address locations of the program memory. An instruction stored in unerasable memory on the chip initiates self-programming of the program memory with the program to be executed by the microcontroller by enabling a pointer timed by the clock to alternately read addresses containing steps of the program to be executed from off-chip memories and to write same into successive addresses of the on-chip program memory by incrementing the latter addresses with each step to be written therein.
Abstract:
A microcontroller (10) is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. The microcontroller (10) includes a power supply (70, 85) for supplying power to the overall device within a predetermined range suitable for its operation, and a clock for supplying a clock frequency to the microcontroller with a stability suitable for precise timing and counting within the device. The microcontroller (10) is selectively reset to prevent it from executing programs and instructions for purposes of generating the control signals, and is maintained in the reset condition despite initiation of a removal from the reset condition, until the power supplied by the power supply (70, 85) is in a predetermined range and the clock frequency supplied by the clock is stable.
Abstract:
A microcontroller (10) fabricated on a semiconductor chip has an on-chip EPROM program memory (17) with programmable EPROM configuration fuses located in a limited number of addresses (32) of the on-chip EPROM program memory, the condition of each of EPROM fuses being defined as blown or not blown according to the value of the bit stored in the respective address on the on-chip EPROM program memory. The operating modes of the microcontroller are configurable by appropriately programming at least some of the EPROM fuses. Testing of the microcontroller in at least some of the operating modes is achieved by using latches outside the on-chip EPROM program memory to emulate the EPROM fuses, while suppressing the capability to set the condition of the EPROM fuses during the testing. Upon completion of the testing, control of the operating modes of the microcontroller is returned to EPROM fuses, and the latches are precluded from further emulating the EPROM fuses.
Abstract:
A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory. The microcontroller operates in any one plurality of operating modes, including a secure microcontroller mode. A plurality of EPROM configuration fuses are mapped into the on-chip EPROM program memory as bits in respective address locations for configuring and protecting the microcontroller program memory from read, verify or write instructions initiated from other than a secure area of the chip. The value of a bit representing one of said fuses reflects the condition of the respective fuse. That condition is observed by reading the value of the respective bit for that fuse stored in the EPROM program memory. The chip security is enabled by configuring the microcontroller in a code protected mode by programming the bits representing the desired fuses in the EPROM program memory to blow or erase each fuse according to the desired configuration.