公开(公告)号：JPH09284094A

公开(公告)日：1997-10-31

申请号：JP21864496

申请日：1996-08-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN EIRIYUU ,  TAI SHIYOUGEN ,  NIN KENI ,  RI KANZUI

IPC: H03H17/02

Abstract: PROBLEM TO BE SOLVED: To provide the digital filter bank device in which the digital filter configuration is simplified by using a minimum scale of the hardware. SOLUTION: A digital filter bank device 10 is configured hierarchically by using a feedback mechanism and operated at a prescribed frequency based on reduction in a multiplex rate mechanism. The digital filter bank device 10 operates a sum of products to generate a filter output signal 41 according to an arithmetic operation and the arithmetic operation is conducted according to a distributed arithmetic algorithm. The use of a minimum scale of the hardware is attained by using the multiplex rate mechanism reduction and the discrete arithmetic algorithm so as to conduct signal processing. The configuration area of the semiconductor device is reduced by using the digital filter bank device.

公开(公告)号：JPH0916281A

公开(公告)日：1997-01-17

申请号：JP15950395

申请日：1995-06-26

Applicant: UNITED MICROELECTRONICS CORP

Inventor： WAN SONNTEIN

IPC: G06F1/04 ,  H01L21/822 ,  H01L27/04 ,  H03K5/26 ,  H03K19/003

Abstract: PURPOSE: To provide an IC chip operation suppressing device capable of preventing the operation of an IC chip in a system having a clock rate exceed ing a prescribed reference clock rate for the chip. CONSTITUTION: The suppressing device has a frequency detector 40 for generating at least one reference frequency. The device compares a system clock 50 with the reference frequency, and when the system clock frequency is more than the reference frequency, prevents the operation of the chip. The device can include an external actuator 20 connected to the detector 40 and allowed to generate a comparison permission signal, actuate the comparing function of the detector 40 and generate a frequency selection signal for selecting one of plural built-in reference frequency values to be compared with system oscillation frequency. When the system oscillation frequency is surely less than the reference frequency, the actuator 20 can be turned off so as not to actuate the comparing function of the detector 40.

公开(公告)号：JP2009124179A

公开(公告)日：2009-06-04

申请号：JP2009042934

申请日：2009-02-25

Applicant: United Microelectronics Corp ,  聯華電子股▲ふん▼有限公司

Inventor： EGUCHI KOHEI ,  MIZUO YUURI

IPC: H01L21/76 ,  H01L27/08 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To a semiconductor device which has a trench-type element separation structure with improved electric characteristics, and to provide its manufacturing method.
SOLUTION: A groove 4 is filled with a first silicon oxide film 6 and heated. A joint 7 formed on the first silicon oxide film 6 is filled with a second silicon oxide film 8 and heated again. Thus, the first silicon oxide film 6 and the second silicon oxide film 8 are made to be high in density, and the groove 4 is filled with them as a rigid element isolation oxide film 9 with an uniform etching rate.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 解决的问题：提供具有改善的电特性的沟槽型元件分离结构的半导体器件，并提供其制造方法。 解决方案：槽4填充有第一氧化硅膜6并加热。 形成在第一氧化硅膜6上的接头7被填充有第二氧化硅膜8并再次加热。 因此，使第一氧化硅膜6和第二氧化硅膜8的密度高，并且以均匀蚀刻速率将沟槽4填充为刚性元件隔离氧化膜9。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP3672752B2

公开(公告)日：2005-07-20

申请号：JP31315898

申请日：1998-11-04

Applicant: ユナイテッド マイクロエレクトロニクス コープUnited Microelectronics Corp.

Inventor： 益 民 ▲黄▼ ,  名 聲 楊 ,  萃 蓉 游

IPC: H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/52

CPC classification number: H01L21/76843 ,  H01L21/3212 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/7684 ,  H01L2221/1031

公开(公告)号：JP3646013B2

公开(公告)日：2005-05-11

申请号：JP32102298

申请日：1998-11-11

Applicant: ユナイテッド マイクロエレクトロニクス コープUnited Microelectronics Corp.

Inventor： 國 泰 ▲黄▼ ,  萃 蓉 游 ,  文 益 謝

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L21/28568 ,  H01L21/3211 ,  H01L27/10852 ,  H01L28/55

Abstract: A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.

公开(公告)号：JP2004342652A

公开(公告)日：2004-12-02

申请号：JP2003134182

申请日：2003-05-13

Applicant: United Microelectronics Corp ,  聯華電子股▲ふん▼有限公司

Inventor： CHO SEIGAKU

IPC: H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a dual damascene structure to solve the problem due to excessive steps in a conventional method.
SOLUTION: The method for manufacturing the dual damascene structure includes the steps: (1) providing a semiconductor substrate; (2) forming a photosensitive material layer having a first absorbance and a second absorbance which are different to a first wavelength light ray and a second wavelength light ray on a semiconductor substrate. (3) forming a first latent pattern by performing a first exposure step on the photosensitive material layer by utilizing the first wavelength light ray; (4) forming a second latent pattern by performing a second exposure step on the photosensitive material layer by utilizing the second wavelength light ray; and (5) forming the dual damascene structure in the photosensitive material layer by removing the first latent pattern and the second latent pattern in the photosensitive material layer simultaneously at the step (4).
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP3587712B2

公开(公告)日：2004-11-10

申请号：JP486399

申请日：1999-01-12

Applicant: ユナイテッド マイクロエレクトロニクス コープUnited Microelectronics Corp.

Inventor： 家 ▲チェン▼ 陳

IPC: H01L21/027 ,  G03F1/42 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To provide an alignment mark structure in which an alignment mark on a wafer is not damaged or deteriorated through CMP process but definite quality of the alignment mark can be sustained visually. SOLUTION: An alignment mark structure having a protective dummy pattern for production of semiconductor is provided wherein the alignment mark on a wafer is protected such that the mark is not damaged definite quality is not deteriorated visually by chemical mechanical polishing(CMP). The alignment mark structure has a scribe line of wafer or an alignment mark 102 formed in the region of a nonconstitutional part, and a protective dummy pattern 114 for protecting it against CMP. The protective dummy pattern 114 has uniform density substantially equal to that of the constitutional part region of the wafer. Since the alignment mark structure protects the alignment mark against damage and prevents the alignment mark from being deteriorated through CMP process, definite quality of the alignment mark 102 can be sustained visually.

公开(公告)号：JP2002058236A

公开(公告)日：2002-02-22

申请号：JP2000213058

申请日：2000-07-13

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RYAN T HIROSE

IPC: H01L27/04 ,  H01L21/822 ,  H02M3/07

Abstract: PROBLEM TO BE SOLVED: To provide a low-power and high-speed dynamic regulation system. SOLUTION: A charge pump includes an input node which is coupled with a power source so as to receive input voltage, and an oscillator unit which generates a cyclic regulator enabling signal and a cyclic reset signal. A regulator clock unit is coupled with the oscillator unit, and it generates a precharge(PC) signal and a regulator reset signal, in answer to the regulator enabling signal, and a pump clock unit generates a plurality of pump clock signal, receiving a master clock signal, and a charge pump unit is coupled with the input node, and is controlled operably by a plurality of pump clock signals, and is coupled with an output terminal so as to generate an output signal (VPUMP), and a regulator unit is coupled so that it may receive the VPUMP signal, the PC signal, the reference signal, and the regulator enabling signal, and it operates in precharge mode or regulation mode, in answer to the regulator enabling signal.

公开(公告)号：JP2002055438A

公开(公告)日：2002-02-20

申请号：JP2000228578

申请日：2000-07-28

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIU EN-CHOAN ,  PON CHAO-RIN ,  LEE TAI-YUAN

IPC: G03F1/00 ,  G03F1/40 ,  H01L21/027 ,  G03F1/14

Abstract: PROBLEM TO BE SOLVED: To provide a discharge protection function by which static charges are discharged into air through discharge peaks by a neutralization discharge reaction to a photomask so as to avoid damage by the neutralization discharge reaction to thin circuit edges of a circuit pattern on the photomask. SOLUTION: The photomask comprises a transparent substrate, a patterned shield layer disposed on a prescribed region of the surface of the substrate and an electrostatic discharge(ESD) protection layer disposed on the surface of the substrate. The ESD protection layer encloses the shield layer and comprises plural discharge peaks used for discharging static electricity into air so as to eliminate electric charges from the photomask.

公开(公告)号：JP2001196497A

公开(公告)日：2001-07-19

申请号：JP2000004880

申请日：2000-01-13

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SEN MEICHI ,  FEN TAISEI ,  KAN SORITSU

IPC: H01L23/12 ,  H01L21/66 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide the structure and the manufacturing method of IC on wafer level, which are useful for improving the yield of the manufacture of IC. SOLUTION: An IC structure on wafer level is formed on a semiconductor wafer and it is formed in a plurality of discrete IC blocks on the wafer. Respective IC blocks are used for forming a plurality of IC components of memory cells. Multilayer wiring structure is formed for electrically connecting the IC components in the IC blocks. For disconnecting an IC component which does not normally operate from active use, a first test and a process of restoration are conducted. This completes the, manufacture stage of a manufacture process. For disconnecting an IC block which does not normally operate from active use even in the stage of packaging, a second test and restoration are conducted.