公开(公告)号：US09893158B2

公开(公告)日：2018-02-13

申请号：US15216889

申请日：2016-07-22

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Oliver Haeberlen

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/408 ,  H01L21/31155 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

Abstract: A semiconductor device is provided that includes a transistor in a semiconductor body having a main surface. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The body region and the drift zone are disposed along a first direction between the source region and the drain region. The first direction is parallel to the main surface. The semiconductor device further includes a field plate disposed in field plate trenches extending along the first direction in the drift zone, and a field dielectric layer between the field plate and the drift zone. A thickness of the field dielectric layer gradually increases along the first direction from a portion adjacent to the source region to a portion adjacent to the drain region.

公开(公告)号：US09882555B2

公开(公告)日：2018-01-30

申请号：US15192523

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Anton Mauder ,  Jens Barrenscheen

IPC: H03K17/06

CPC classification number: H03K17/063 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7813 ,  H01L29/7815 ,  H03K17/18 ,  H03K2017/6878

Abstract: A switch is provided having a switch transistor as well as a monitoring component to monitor a control signal applied to the switch transistor. With the monitoring component, in some implementation a monitoring of the control signal independent from a load path may be possible.

公开(公告)号：US20170373685A1

公开(公告)日：2017-12-28

申请号：US15192473

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Anton Mauder ,  Jens Barrenscheen

IPC: H03K17/687 ,  H03K7/08

CPC classification number: H03K17/687 ,  H01L29/00 ,  H03K7/08 ,  H03K17/18 ,  H03K2017/6878

Abstract: Switch devices using switch transistors with dual gates are provided. The dual gates may be controlled independently from each other by first and second gate driver circuits.

公开(公告)号：US20170373678A1

公开(公告)日：2017-12-28

申请号：US15192523

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Anton Mauder ,  Jens Barrenscheen

IPC: H03K17/06

CPC classification number: H03K17/063 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7813 ,  H01L29/7815 ,  H03K17/18 ,  H03K2017/6878

Abstract: A switch is provided having a switch transistor as well as a monitoring component to monitor a control signal applied to the switch transistor. With the monitoring component, in some implementation a monitoring of the control signal independent from a load path may be possible.

公开(公告)号：US09853637B1

公开(公告)日：2017-12-26

申请号：US15192473

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Anton Mauder ,  Jens Barrenscheen

IPC: H03K17/687 ,  H03K7/08

CPC classification number: H03K17/687 ,  H01L29/00 ,  H03K7/08 ,  H03K17/18 ,  H03K2017/6878

Abstract: Switch devices using switch transistors with dual gates are provided. The dual gates may be controlled independently from each other by first and second gate driver circuits.

公开(公告)号：US20170317176A1

公开(公告)日：2017-11-02

申请号：US15646152

申请日：2017-07-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L27/12

CPC classification number: H01L29/4175 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7826 ,  H01L29/7835

Abstract: A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

公开(公告)号：US20170301791A1

公开(公告)日：2017-10-19

申请号：US15484206

申请日：2017-04-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Detlef Weber ,  Karl-Heinz Gebhardt

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L21/26586 ,  H01L21/823418 ,  H01L27/0623 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7835

Abstract: A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.

公开(公告)号：US09614064B2

公开(公告)日：2017-04-04

申请号：US14673072

申请日：2015-03-30

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser

IPC: H01L29/78 ,  H01L29/735 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/808 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/41766 ,  H01L29/42304 ,  H01L29/4236 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/785 ,  H01L29/808

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a body region, and a gate electrode structure adjacent to the body region. The source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface. The body region is disposed between the source region and the drain region. The body region includes an upper body region at the main surface and a lower body region remote from the main surface. A first width of the lower body region is smaller than a second width of the upper body region. The first width and the second width are measured in a direction perpendicular to the first direction.

公开(公告)号：US09608070B2

公开(公告)日：2017-03-28

申请号：US15139758

申请日：2016-04-27

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/4175 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/156 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835

Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.

公开(公告)号：US09570576B2

公开(公告)日：2017-02-14

申请号：US14102290

申请日：2013-12-10

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Anton Mauder ,  Markus Zundel ,  Hans-Joachim Schulze ,  Franz Hirler ,  Hans Weber

IPC: H01L21/332 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L21/768 ,  H01L29/739 ,  H01L29/78 ,  H01L29/40 ,  H01L29/861

CPC classification number: H01L29/66333 ,  H01L21/02118 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/30604 ,  H01L21/76831 ,  H01L21/76898 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/861

Abstract: A method for forming a semiconductor device includes forming an electrical structure at a main surface of a semiconductor substrate and carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate.

Abstract translation: 一种形成半导体器件的方法包括在半导体衬底的主表面上形成电结构，并对半导体衬底的背面表面的背面表面区进行阳极氧化，以在后侧形成氧化物层 半导体衬底的表面。