公开(公告)号：US09484309B2

公开(公告)日：2016-11-01

申请号：US14419841

申请日：2013-07-11

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Toshio Hata ,  Makoto Agatani ,  Shinya Ishizaki ,  Makoto Matsuda ,  Tomokazu Nada ,  Toyonori Uemura

IPC: H01L23/544 ,  G03F9/00 ,  H01L33/60 ,  H01L25/075 ,  H01L33/62 ,  H05K1/02 ,  H05K3/12 ,  H05K3/28

CPC classification number: H01L33/60 ,  G03F9/7073 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/62 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/45144 ,  H01L2224/48137 ,  H05K1/0269 ,  H05K3/12 ,  H05K3/28 ,  H05K2201/09918 ,  H05K2201/09936 ,  H01L2924/00

Abstract: A light emitting device (10) includes light emitting elements (12), conductor wirings (14), and alignment marks (18) formed on a substrate (11). The alignment marks (18) and the conductor wirings (14) are formed by printing.

Abstract translation: 发光器件（10）包括发光元件（12），导体布线（14）和形成在基板（11）上的对准标记（18）。 对准标记（18）和导体布线（14）通过印刷形成。

公开(公告)号：US20140110152A1

公开(公告)日：2014-04-24

申请号：US13777056

申请日：2013-02-26

Applicant: FUKUI PRECISION COMPONENT (SHENZHEN) CO., LTD. ,  ZHEN DING TECHNOLOGY CO., LTD.

Inventor： QING ZUO ,  BIN-QIN LUO

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K3/00 ,  H05K1/0269 ,  H05K1/0298 ,  H05K2201/0108 ,  H05K2201/09063 ,  H05K2201/09936 ,  Y10T156/1056

Abstract: A printed circuit board includes a first outer electrically conductive pattern layer, a first insulation layer, a first inner electrically conductive pattern layer, a connection adhesive sheet, a second inner electrically conductive layer, a second insulation layer, a second outer electrically conductive pattern layer, and a identification mark, which are arranged in that order. The first outer electrically conductive pattern layer includes many first gold fingers. The second outer electrically conductive pattern layer includes many second gold fingers. The blind hole corresponds to the identification mark. The first outer electrically conductive pattern layer, the second outer electrically conductive pattern layer, and the at least one identification mark are simultaneously formed.

Abstract translation: 印刷电路板包括第一外部导电图案层，第一绝缘层，第一内部导电图案层，连接粘合片，第二内部导电层，第二绝缘层，第二外部导电图案层 ，以及以该顺序排列的识别标记。 第一外部导电图案层包括许多第一金指。 第二外导电图案层包括许多第二金指。 盲孔对应于识别标记。 同时形成第一外部导电图案层，第二外部导电图案层和至少一个识别标记。

公开(公告)号：US08694148B2

公开(公告)日：2014-04-08

申请号：US11719390

申请日：2005-11-14

Applicant: Michael Tyler ,  Robert W. Colby ,  Jeffrey W. Leonard ,  Lindsey M. Dotson ,  David A. Watt ,  Cris E. Hill ,  Laura H. Campbell

Inventor： Michael Tyler ,  Robert W. Colby ,  Jeffrey W. Leonard ,  Lindsey M. Dotson ,  David A. Watt ,  Cris E. Hill ,  Laura H. Campbell

IPC: G06F19/00 ,  G01R31/00

CPC classification number: H05K3/0026 ,  B23K26/02 ,  B23K26/382 ,  B23K26/389 ,  B23K26/40 ,  B23K31/12 ,  B23K2101/42 ,  B23K2103/12 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  H05K3/225 ,  H05K2201/09936 ,  H05K2203/163

Abstract: A method and system increase processed specimen yield in the laser processing of target material that includes multiple specimens formed on a common substrate. Preferred embodiments implement a feature that enables storage in the laser processing system a list of defective specimens that have somehow been subject to error during laser processing. Once the common substrate has been completely processed, the system alerts an operator to the number of improperly processed specimens and gives the operator an opportunity to run a software routine, which in a preferred embodiment uses a laser to scribe a mark on the top surface of each improperly processed specimen.

Abstract translation: 一种方法和系统在目标材料的激光加工中增加了加工样品产量，其包括在公共基底上形成的多个样品。 优选实施例实现能够在激光处理系统中存储在激光处理期间以某种方式遭受错误的缺陷样本的列表的特征。 一旦共同的基板被完全处理，系统就会向操作人员提供不正确处理的标本的数量，并给予操作者运行一个软件程序的机会，在一个优选的实施例中，该程序使用激光来刻划在 每个不正确加工的样品。

公开(公告)号：US20130319745A1

公开(公告)日：2013-12-05

申请号：US13519374

申请日：2012-06-11

Applicant: Hua Zheng ,  Cheng-hung Chen

Inventor： Hua Zheng ,  Cheng-hung Chen

IPC: H05K1/11

CPC classification number: H05K1/0269 ,  H05K1/0289 ,  H05K2201/09281 ,  H05K2201/09936

Abstract: The present invention provides a routing structure and display panel. The routing structure includes a plurality of routing, disposed separately. Each routing corresponds to a symbol, and the symbol is disposed on the routing to act as a part of the routing to conduct electricity. In this manner, the routing structure and display panel of the present invention allow expansion of routing width, effectively reduce RC constant and energy-consumption, and improve yield rate.

Abstract translation: 本发明提供一种路由结构和显示面板。 路由结构包括多个路由，分开设置。 每个路由对应于符号，并且该符号被布置在路由上以充当路由的一部分以进行电力。 以这种方式，本发明的路由结构和显示面板允许扩展路由宽度，有效降低RC常数和能量消耗，并提高成品率。

公开(公告)号：US08584924B2

公开(公告)日：2013-11-19

申请号：US10506611

申请日：2003-03-06

Applicant: Jürgen Schulz-Harder

Inventor： Jürgen Schulz-Harder

IPC: B23K20/24

CPC classification number: C04B37/021 ,  B32B2311/12 ,  C04B2237/407 ,  H05K1/0266 ,  H05K1/0306 ,  H05K3/061 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/38 ,  H05K3/383 ,  H05K2201/0355 ,  H05K2201/09909 ,  H05K2201/09936 ,  H05K2203/0369 ,  H05K2203/0571 ,  H05K2203/0588

Abstract: The invention relates to a novel process for producing a metal ceramic substrate, especially a copper-ceramic substrate, in which at least one metal foil at a time is applied to the surface sides of a ceramic layer or a ceramic substrate using a high temperature bonding process and the metal foil is structured on at least one surface side for forming conductive tracks, contact surfaces, and the like.

Abstract translation: 本发明涉及一种用于制造金属陶瓷基板，特别是铜陶瓷基板的新方法，其中使用高温接合将至少一个金属箔一次施加到陶瓷层或陶瓷基板的表面侧 工艺，并且金属箔被构造在用于形成导电轨道，接触表面等的至少一个表面侧上。

公开(公告)号：US20130186960A1

公开(公告)日：2013-07-25

申请号：US13553997

申请日：2012-07-20

Applicant: Hidetoshi SUZUKI ,  Yuichi Hotta ,  Yuji Shimoda ,  Yuuji Ogawa ,  Taku Nishiyama ,  Tadanobu Okubo ,  Junichi Onodera ,  Takeshi Ikuta ,  Naohisa Okumura ,  Katsuyoshi Watanabe ,  Kazuhide Doi

Inventor： Hidetoshi SUZUKI ,  Yuichi Hotta ,  Yuji Shimoda ,  Yuuji Ogawa ,  Taku Nishiyama ,  Tadanobu Okubo ,  Junichi Onodera ,  Takeshi Ikuta ,  Naohisa Okumura ,  Katsuyoshi Watanabe ,  Kazuhide Doi

IPC: G06K19/077

CPC classification number: G06K19/07732 ,  H01L23/3107 ,  H01L23/49838 ,  H01L23/49855 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/165 ,  H01L25/18 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0259 ,  H05K1/0269 ,  H05K1/113 ,  H05K1/117 ,  H05K3/284 ,  H05K3/321 ,  H05K2201/09563 ,  H05K2201/0979 ,  H05K2201/09936 ,  H05K2201/10287 ,  H05K2203/1327 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: According to one embodiment, a semiconductor storage device is provided with a memory chip including a storage circuit, a controller chip that controls a memory chip, and a substrate having a first surface and a second surface opposing one another, on the first surface of which the controller chip is mounted. Further, the semiconductor storage device is provided with an external connection terminal formed on the second surface of the substrate, and resin that encapsulates the memory chip, the controller chip, and the substrate, includes a third surface and a fourth surface opposing one another, and has a predetermined mark directly printed only on the fourth surface that is adjacent to the second surface of the substrate.

Abstract translation: 根据一个实施例，半导体存储装置设置有存储芯片，存储芯片包括存储电路，控制存储芯片的控制器芯片和具有第一表面和第二表面的基板，第一表面和第二表面在其第一表面上 安装控制器芯片。 此外，半导体存储装置设置有形成在基板的第二表面上的外部连接端子，并且封装存储芯片，控制器芯片和基板的树脂包括彼此相对的第三表面和第四表面， 并且具有仅在与基板的第二表面相邻的第四表面上直接印刷的预定标记。

公开(公告)号：US20130033284A1

公开(公告)日：2013-02-07

申请号：US13647585

申请日：2012-10-09

Applicant: SanDisk Technologies Inc.

Inventor： Arie Frenklakh

IPC: G01R31/26

CPC classification number: H05K1/0268 ,  G06K7/0095 ,  G06K19/07 ,  G06K19/07732 ,  G11C29/1201 ,  G11C29/48 ,  H01L22/34 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1433 ,  H01L2924/181 ,  H05K1/0275 ,  H05K2201/09936 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads.

公开(公告)号：US08283664B2

公开(公告)日：2012-10-09

申请号：US13041895

申请日：2011-03-07

Applicant: Arie Frenklakh

Inventor： Arie Frenklakh

IPC: H01L23/58 ,  H01L29/10

CPC classification number: H05K1/0268 ,  G06K7/0095 ,  G06K19/07 ,  G06K19/07732 ,  G11C29/1201 ,  G11C29/48 ,  H01L22/34 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1433 ,  H01L2924/181 ,  H05K1/0275 ,  H05K2201/09936 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads.

Abstract translation: 公开了一种形成半导体封装的方法，包括伪装测试焊盘。 测试焊盘被限定在半导体封装的导电图案中，用于允许完成封装的电测试。 测试垫形成为诸如字母或物体的形状，使得它们不太可识别为测试垫。

公开(公告)号：US20120087099A1

公开(公告)日：2012-04-12

申请号：US13195289

申请日：2011-08-01

Applicant: Taeho Moon ,  Whasu Sin ,  Junsoo Han ,  Jee-Min Park

Inventor： Taeho Moon ,  Whasu Sin ,  Junsoo Han ,  Jee-Min Park

IPC: H05K7/02

CPC classification number: H05K1/0269 ,  H01L23/13 ,  H01L23/544 ,  H01L24/48 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/0052 ,  H05K2201/09936 ,  H05K2201/10159 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided is a printed circuit board for a board-on-chip package prepared with a strip level of a plurality of unit substrates and including a reject marking portion for determining whether there is a defective unit substrate, wherein the reject marking portion is in each unit substrate.

Abstract translation: 提供了一种用于片上芯片封装的印刷电路板，其制备有多个单元基板的带状层，并且包括用于确定是否存在缺陷单元基板的拒收标记部分，其中拒收标记部分在每个单元中 基质。

公开(公告)号：US08097816B2

公开(公告)日：2012-01-17

申请号：US12661494

申请日：2010-03-18

Applicant: Keiichi Sugimoto ,  Mitsuru Nakagawa

Inventor： Keiichi Sugimoto ,  Mitsuru Nakagawa

IPC: H01L23/28

CPC classification number: H05K3/284 ,  H05K3/281 ,  H05K5/0243 ,  H05K5/065 ,  H05K2201/09936 ,  H05K2203/1311 ,  H05K2203/1316 ,  H05K2203/1322 ,  Y10T29/49124 ,  Y10T29/49146

Abstract: A method of producing an electronic device includes a holding of a circuit board and a decoration sheet in a cavity of a mold, and a filling and solidifying of thermosetting resin in the cavity. A casing is molded by the solidified thermosetting resin so as to seal electronic parts and a first face of the circuit board having the electronic parts. Further, the decoration sheet is integrated with the casing by the solidified thermosetting resin. An outer surface of the casing is defined by a second face of the circuit board opposite from the first face and the decoration sheet.

Abstract translation: 电子设备的制造方法包括在模具的空腔中保持电路板和装饰片，以及在空腔中填充和固化热固性树脂。 通过凝固的热固性树脂模制套管，以密封电子部件和具有电子部件的电路板的第一面。 此外，装饰片通过凝固的热固性树脂与壳体一体化。 壳体的外表面由电路板的与第一面和装饰片相对的第二面限定。