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公开(公告)号：US20220286319A1
公开(公告)日：2022-09-08
申请号：US17677113
申请日：2022-02-22
Inventor： Fred Rennig , Vaclav Dvorak
IPC: H04L12/403 , G06F9/30
Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.
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公开(公告)号：US11366778B2
公开(公告)日：2022-06-21
申请号：US16874055
申请日：2020-05-14
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40 , G06F11/07 , H04L12/403 , G05B19/042 , H03M13/09
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US11360143B2
公开(公告)日：2022-06-14
申请号：US17083876
申请日：2020-10-29
Applicant: STMicroelectronics International N.V. , STMicroelectronics Application GmbH , STMicroelectronics S.r.l.
Inventor： Avneep Kumar Goyal , Deepak Baranwal , Thomas Szurmant , Nicolas Bernard Grossier
IPC: G01R31/317 , G01R31/3185 , G01R31/3193 , G06F11/34 , G01R31/319 , G06F11/36
Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.
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公开(公告)号：US11210161B2
公开(公告)日：2021-12-28
申请号：US16928768
申请日：2020-07-14
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Roberta Vittimani
Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
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公开(公告)号：US20210357538A1
公开(公告)日：2021-11-18
申请号：US17443497
申请日：2021-07-27
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Giovanni Disirio
IPC: G06F21/83 , G06F21/64 , G06F12/02 , G06F9/38 , G06F9/445 , H04L9/32 , G06F21/57 , G09C1/00 , G06F21/74 , H04W12/106
Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.
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Patent Agency Ranking
公开(公告)号：US20210294534A1
公开(公告)日：2021-09-23
申请号：US17341054
申请日：2021-06-07
Inventor： Roberto Colombo , Om Ranjan
Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration data client.
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157.发明授权公开(公告)号：US11068331B2
公开(公告)日：2021-07-20
申请号：US16289425
申请日：2019-02-28
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
Abstract: A processing system includes a processing unit configured to be connected to a memory with error detection and/or correction. The processing unit generates at least one read request for reading data from the memory, the read request including an address signal identifying an address of a given memory area in the memory. The processing system includes an error handling circuit connected to the memory for receiving an error signal containing an error code indicating whether the data read from the memory contains errors. The error handling circuit includes a hardware circuit configured to set a first error signal to the error code of the error signal when the address indicated by the address signal belongs to a first address range and to set a second error signal to the error code of the error signal when the address indicated by the address signal belongs to a second address range.
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公开(公告)号：US11031672B2
公开(公告)日：2021-06-08
申请号：US16521757
申请日：2019-07-25
Inventor： Petr Ourednik , Yvon Gourdou
Abstract: An antenna includes two planar coils that are mechanically disposed face to face and electrically connected in series. The antenna is mounted to a disposable consumer product (for example, a cartridge for use with an electronic cigarette). The antenna is configured to support near field communications with a reader circuit for purposes of authenticating use of the disposable consumer product.
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公开(公告)号：US10754723B2
公开(公告)日：2020-08-25
申请号：US15975507
申请日：2018-05-09
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Roberta Vittimani
Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
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公开(公告)号：US10740041B2
公开(公告)日：2020-08-11
申请号：US15991208
申请日：2018-05-29
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
Abstract: A processing system includes a processing unit and a hardware block configured to change operation as a function of life cycle data. A one-time programmable memory includes original life cycle data. A hardware configuration module is configured to read the original life cycle data from the one-time programmable memory and provide the original life cycle data to the hardware block. The hardware configuration module includes a register providing the life cycle data used to change operation of the hardware block. The hardware configuration module is configured to store the original life cycle data in the register and receive a command from the processing unit. The command includes a write request for storing new life cycle data in the register.
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