公开(公告)号：US20150041955A1

公开(公告)日：2015-02-12

申请号：US14077512

申请日：2013-11-12

Applicant: Apple Inc.

Inventor： Jared L. Zerbe ,  Emerson S. Fang ,  Jun Zhai ,  Shawn Searles

IPC: H01L27/10 ,  H01L23/48

CPC classification number: H01L27/101 ,  H01G4/228 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

Abstract translation: 描述了包括电力消耗装置（例如SOC装置）的半导体器件封装。 电力消耗装置可以包括一个或多个电流消耗元件。 无源设备可以耦合到功率消耗设备。 无源器件可以包括形成在半导体衬底上的多个无源元件。 无源元件可以布置在半导体衬底上的结构阵列中。 功率消耗装置和无源装置可以使用一个或多个终端来耦合。 无源器件和功耗器件耦合可以被配置成使得功率消耗器件功能地确定无源器件元件将被使用的方式。

公开(公告)号：US20140084487A1

公开(公告)日：2014-03-27

申请号：US13627905

申请日：2012-09-26

Applicant: APPLE INC.

Inventor： Jie-Hua Zhao ,  Yizhang Yang ,  Jun Zhai ,  Chih-Ming Chung

IPC: H01L23/52 ,  H01L21/50

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  Y02P80/30 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages.

Abstract translation: PoP（封装封装）封装包括一个耦合到顶部封装的底部封装。 底部封装顶部的端子通过位于底部封装的上表面和顶部封装的下表面之间的电绝缘材料耦合到顶部封装的底部上的端子。 底部包装和顶部包装在加工包装的过程中被联接，该过程中施加力以使包装在一起。

公开(公告)号：US20250157939A1

公开(公告)日：2025-05-15

申请号：US19023078

申请日：2025-01-15

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

公开(公告)号：US20250149489A1

公开(公告)日：2025-05-08

申请号：US19015233

申请日：2025-01-09

Applicant: Apple Inc.

Inventor： Jared L. Zerbe ,  Emerson S. Fang ,  Jun Zhai ,  Shawn Searles

IPC: H01L23/00 ,  H01G4/228 ,  H01L23/13 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L25/18 ,  H10B12/00 ,  H10D1/68

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

公开(公告)号：US20250029921A1

公开(公告)日：2025-01-23

申请号：US18792451

申请日：2024-08-01

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L23/528 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L23/58 ,  H01L25/065

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US20240421013A1

公开(公告)日：2024-12-19

申请号：US18585834

申请日：2024-02-23

Applicant: Apple Inc.

Inventor： Jixuan Gong ,  Vidhya Ramachandran ,  Jie-Hua Zhao ,  Young Doo Jeon ,  Wei Chen ,  Jun Zhai

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/58

Abstract: Integrated circuit (IC) structure, IC die structures and methods of fabrication are described in which one or more edge recesses are formed in an IC die. Upon direct bonding to an electronic component, a molding compound can be applied to the bonded structure where the molding compound fills the one or more edge recesses and encroached underneath the IC die and between the IC die and the electronic component.

公开(公告)号：US12159835B2

公开(公告)日：2024-12-03

申请号：US18339102

申请日：2023-06-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18 ,  H01L23/00

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US20240387390A1

公开(公告)日：2024-11-21

申请号：US18671478

申请日：2024-05-22

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai

IPC: H01L23/538 ,  H01L21/66 ,  H01L23/00 ,  H01L23/488 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/18

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US12119275B2

公开(公告)日：2024-10-15

申请号：US17461207

申请日：2021-08-30

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jie-Hua Zhao ,  Jun Zhai

IPC: H01L23/053 ,  H01L23/10

CPC classification number: H01L23/053 ,  H01L23/10

Abstract: Modules and methods of assembly are described. A module includes a lid mounted on a module substrate and covering a component. A stiffener structure may optionally be mounted between the lid and module substrate. A recess can be formed in any of an outer wall bottom surface of the lid, and top or bottom surface of the stiffener structure such that an adhesive layer at least partially fills the recess.

公开(公告)号：US12033982B2

公开(公告)日：2024-07-09

申请号：US17457350

申请日：2021-12-02

Applicant: Apple Inc.

Inventor： Jun Zhai

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L2224/05009 ,  H01L2225/06513

Abstract: Reconstructed 3DIC structures and methods of manufacture are described. In an embodiment, one or more dies in each package level of a 3DIC are both functional chips and/or stitching devices for two or more dies in an adjacent package level. Thus, each die can function as a communication bridge between two other dies/chiplets in addition to performing a separate chip core function.