公开(公告)号：WO0182085A2

公开(公告)日：2001-11-01

申请号：PCT/US0140573

申请日：2001-04-23

Applicant: SUN MICROSYSTEMS INC

Inventor： WEEK JEREMY

IPC: G06F11/34

CPC classification number: G06F11/3466 ,  G06F11/3409 ,  G06F2201/88 ,  G06F2201/885

Abstract: In accordance with methods and systems consistent with the present invention, an improved processor performance instrumentation system is provided that allows a software tester to measure more performance indicators and there are hardware counters during a single execution of a tested program. The improved processor performance instrumentation system accomplishes this by "multiplexing" performance indicators while executing the tested program. In effect, methods and systems consistent with the present invention extend the abilities of the limited number of hardware counters to allow them to measure a number of performance indicators otherwise not allowed during one execution of the tested program.

Abstract translation: 根据与本发明一致的方法和系统，提供了一种改进的处理器性能仪器系统，其允许软件测试器测量更多的性能指标，并且在单个执行测试程序期间存在硬件计数器。 改进的处理器性能测量系统通过在执行测试程序时“复用”性能指标来实现这一点。 实际上，与本发明一致的方法和系统扩展了有限数量的硬件计数器的能力，以允许它们测量在一次执行测试程序期间不允许的许多性能指标。

公开(公告)号：WO01061499A1

公开(公告)日：2001-08-23

申请号：PCT/SE2001/000223

申请日：2001-02-07

IPC: G06F11/34 ,  G06F12/08

CPC classification number: G06F9/5016 ,  G06F11/3409 ,  G06F12/0802 ,  G06F2201/88 ,  G06F2201/885

Abstract: The present invention discloses a processor system comprising a processor (31) and at least a first memory (32) and a second memory (34, 36, 37). The first memory (32) is normally faster than the second one, and means for memory allocation (38, 41, 48) perform the periodically static allocation of data into the first memory (32). The means for memory allocation (38, 41, 48) are run-time updateable by software. An execution profiling section (39) is provided for continuously or intermittently providing execution data used for updating the means for memory allocation (38, 41, 48). According to the invention, the memory allocation is performed on a variable or record (49, 50) level. The means for memory allocation preferably use linking tables (41, 48) supporting dynamic software changes. The first memory (32) is preferably an SRAM, connected to the processor by a dedicated bus (33).

Abstract translation: 本发明公开了一种包括处理器（31）和至少第一存储器（32）和第二存储器（34,36,37）的处理器系统。 第一存储器（32）通常比第二存储器（32）快，并且用于存储器分配（38,41,48）的装置执行数据到第一存储器（32）的周期性静态分配。 内存分配（38,41,48）的运行时间可由软件更新。 提供执行分析部分（39）用于连续地或间歇地提供用于更新用于存储器分配的装置（38,41,48）的执行数据。 根据本发明，对变量或记录（49,50）进行存储器分配。 用于存储器分配的装置优选地使用支持动态软件改变的链接表（41,48）。 第一存储器（32）优选地是通过专用总线（33）连接到处理器的SRAM。

公开(公告)号：WO00068796A1

公开(公告)日：2000-11-16

申请号：PCT/US2000/012620

申请日：2000-05-09

IPC: G06F11/34 ,  G06F12/08

CPC classification number: G06F11/3457 ,  G06F12/0802 ,  G06F2201/885

Abstract: A method of selecting a cache design for a computer system begins with the making (S11) of a prototype module with a processor (15), a "seed" cache (17), and a trace detection module (31). The prototype module can be inserted within a system that includes main memory (23) and peripherals (25). While an application program is run (S21) on the system, the communications between the processor and the seed cache are detected (S22) and compressed (S23). The compressed detections are stored (S24) in a trace capture module and collectively define a trace of the program on the prototype module. Then trace is then expanded (S31) and used to evaluate (S32) a candidate cache design. The expansion and evaluation can be iterated to evaluate many cache designs. The method can be used to pick the cache design with the best performance or as a foundation for performing a cost/performance comparison of the evaluated caches. In this method, a single prototype is used to generate an accurate trace that permits many alternative cache designs to be evaluated. This contrasts with methods that use cacheless models to develop less accurate traces and methods that allow only one cache design to be evaluated per prototype. In summary, the invention provides an accurate and efficient method of evaluating alternative cache designs.

Abstract translation: 选择用于计算机系统的高速缓存设计的方法开始于具有处理器（15），“种子”高速缓存（17）和跟踪检测模块（31）的原型模块的（S11）。 原型模块可以插入到包括主存储器（23）和外围设备（25）的系统内。 当在系统上运行应用程序（S21）时，检测处理器和种子高速缓存之间的通信（S22）并进行压缩（S23）。 将压缩检测（S24）存储在跟踪捕获模块中，并共同定义原型模块上程序的跟踪。 然后跟踪扩展（S31），并用于评估（S32）候选缓存设计。 可以迭代扩展和评估来评估许多缓存设计。 该方法可用于选择具有最佳性能的缓存设计或作为执行评估的缓存的成本/性能比较的基础。 在该方法中，使用单个原型来生成允许评估许多备用高速缓存设计的精确跟踪。 这与使用无高速缓存模型开发不太准确的跟踪和方法的方法形成对比，只允许每个原型对一个缓存设计进行评估。 总之，本发明提供了一种评估替代缓存设计的准确和有效的方法。

公开(公告)号：WO0013078A9

公开(公告)日：2000-10-12

申请号：PCT/US9918601

申请日：1999-08-16

Applicant: EMC CORP

Inventor： BACHMAT EITAN ,  OFEK YUVAL

IPC: G06F3/06 ,  G06F11/34 ,  G06F12/00 ,  G11B17/22

CPC classification number: G06F3/061 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0689 ,  G06F11/3433 ,  G06F11/3452 ,  G06F11/3485 ,  G06F2201/88 ,  G06F2201/885 ,  G11B17/22

Abstract: Load balancing of activities on physical disk storage devices is accomplished by monitoring reading and writing operations to blocks of contiguous storage locations on the physical disk storage devices. A list of exchangeable pairs of blocks is developed based on size and function. Statistics accumulated over an interval are then used to obtain access activity values for each block and each physical disk drive. A statistical analysis leads to a selection of one block pair. After testing to determine any adverse effect of making that change, the exchange is made to more evenly distribute the loading on individual physical disk storage devices.

Abstract translation: 物理磁盘存储设备上活动的负载平衡通过监视对物理磁盘存储设备上连续存储位置块的读写操作来完成。 根据尺寸和功能开发可交换块对列表。 然后使用一段时间内累积的统计信息来获取每个块和每个物理磁盘驱动器的访问活动值。 统计分析导致选择一个块对。 经过测试以确定进行此更改的任何不利影响后，交换机将更均匀地分配各个物理磁盘存储设备上的负载。

公开(公告)号：WO98045784A1

公开(公告)日：1998-10-15

申请号：PCT/US1998/006838

申请日：1998-04-07

IPC: G06F11/26 ,  G06F11/28 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F11/3612 ,  G06F11/261 ,  G06F11/3419 ,  G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: A processor-based device (102) incorporating an on-chip trace cache (200) and supporting circuitry for providing software performance profiling information. A trigger control register (219a) is configured to initialize and trigger (start) a first on-chip counter upon entry into a selected procedure. A second trigger control register (219b) is used to stop the first counter when the procedure prologue of the selected procedure is entered. Counter values reflecting the lapsed execution time of the selected procedure are then stored in the on-chip trace cache. A second counter is also provided. The second counter runs continually, but is reset to zero following a stop trigger event caused by the second trigger control register. The stop trigger event also causes the value of the second counter to be placed in the on-chip trace cache (200). This second counter value provides the frequency of occurence of a procedure of interest, whereas the first counter provides information about the procedure's execution time. Either post-processing software executing on a target system, a host system utilizing a debug port, or off-chip trace capture hardware can be used to analyze the profile data.

Abstract translation: 一种基于处理器的设备（102），其结合有片上跟踪高速缓存（200）和用于提供软件性能分析信息的支持电路。 触发控制寄存器（219a）被配置为在进入所选择的过程时初始化和触发（启动）第一片上计数器。 当输入所选程序的过程序列时，第二个触发控制寄存器（219b）用于停止第一个计数器。 反映所选程序的经过的执行时间的计数器值然后存储在片上跟踪高速缓存中。 还提供了第二个计数器。 第二个计数器连续运行，但是在由第二个触发控制寄存器引起的停止触发事件之后复位为零。 停止触发事件还使得第二计数器的值被放置在片上跟踪高速缓存（200）中。 该第二计数器值提供感兴趣的程序的发生频率，而第一计数器提供关于过程的执行时间的信息。 可以使用在目标系统上执行的后处理软件，利用调试端口的主机系统或片外跟踪捕获硬件来分析简档数据。

公开(公告)号：WO98045783A1

公开(公告)日：1998-10-15

申请号：PCT/US1998/006837

申请日：1998-04-07

IPC: G06F11/28 ,  G06F11/26 ,  G06F11/34 ,  G06F11/36 ,  G06F11/00

CPC classification number: G06F11/3636 ,  G06F11/261 ,  G06F11/3419 ,  G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: A processor-based device (102) incorporating an on-chip instruction trace cache (200) capable of providing information for reconstructing instruction execution flow. The trace information can be captured without halting normal processor (104) operation. Both serial (204) and parallel (214) communication channels are provided for communicating the trace information to external devices. In the disclosed embodiment of the invention, instructions that disrupt the instruction flow are reported, particularly instructions in which the target address is in some way data dependent. For example, call instructions or unconditional branch instructions in which the target address is provided from a data register (or other memory location such as a stack) cause a trace cache entry to be generated. In the case of many unconditional branches or sequential instructions, no entry is placed into the trace cache (200) because the target address can be completely determined from the instruction stream. Other information provided by the instructiontrace cache (200) includes: the target address of a trap or interrupt handler, the target address of a return instruction, addresses from procedure returns, task identifiers, and trace capture stop/start information.

Abstract translation: 一种基于处理器的设备（102），其包含能够提供用于重建指令执行流的信息的片上指令跟踪高速缓存（200）。 可以捕获跟踪信息而不停止正常的处理器（104）操作。 提供串行（204）和并行（214）通信信道用于将跟踪信息传送到外部设备。 在所公开的本发明的实施例中，报告了指令流程中断的指令，特别是目标地址在某种程度上依赖于数据的指令。 例如，从数据寄存器（或诸如堆栈的其他存储器位置）提供目标地址的调用指令或无条件分支指令导致生成跟踪高速缓存条目。 在许多无条件分支或顺序指令的情况下，由于可以从指令流完全确定目标地址，因此不会将任何条目放入跟踪高速缓存（200）。 指令跟踪缓存（200）提供的其他信息包括：陷阱或中断处理程序的目标地址，返回指令的目标地址，来自过程返回的地址，任务标识符和跟踪捕获停止/启动信息。

公开(公告)号：WO1997010548A1

公开(公告)日：1997-03-20

申请号：PCT/US1996014568

申请日：1996-09-11

Applicant: MCSB TECHNOLOGY CORPORATION

Inventor： MCSB TECHNOLOGY CORPORATION ,  SHEETS, Kitrick ,  THOMPSON, Keith

IPC: G06F13/00

CPC classification number: G06F11/3409 ,  G06F11/3433 ,  G06F11/3466 ,  G06F11/3495 ,  G06F2201/885

Abstract: A performance enhancement system including a software implemented in a Performance Assistant File System (PAFS, 52) to enable an efficient and economical performance evaluation and tuning of data servers (58, 60, 62, 64) and networks is disclosed. The PAFS of the present invention is a subcomponent of a performance assistant (PA, 72, 74) architecture which includes a set of powerful software tools (54) that help the user/system administrator tune a computer system to yield maximum performance. Specifically, the present invention enables the user to diagnose and tune operating systems without the need for utilizing laboratory conditions and tools such that the full potential of the processors architecture could be realized.

Abstract translation: 公开了一种性能增强系统，其包括在性能助理文件系统（PAFS，52）中实现的软件，以实现对数据服务器（58,60,62,64）和网络的高效和经济的性能评估和调优。 本发明的PAFS是性能助理（PA，72,74）架构的子部件，其包括一组强大的软件工具（54），其帮助用户/系统管理员调整计算机系统以产生最大性能。 具体地，本发明使得用户能够诊断和调整操作系统，而不需要利用实验室条件和工具，使得可以实现处理器架构的全部潜力。

公开(公告)号：WO2017142562A1

公开(公告)日：2017-08-24

申请号：PCT/US2016/018759

申请日：2016-02-19

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： BENEDICT, Melvin K.

IPC: G06F11/30 ,  G06F12/08

CPC classification number: G06F11/30 ,  G06F11/3037 ,  G06F11/3423 ,  G06F12/08 ,  G06F2201/885

Abstract: Various examples described herein provide for deferred write back based on age time. According to some examples, an age time for a cached instance stored on a data cache is monitored and, based on the age time, a cache table entry for the cached instance may be modified to indicate that the cached instance is a candidate for a deferred write back period. A controller may monitor for a deferred write back period based on data activity of the data cache. During a deferred write back period, the cached instance may be written back from volatile memory to the non-volatile memory based on whether the cache table entry indicates that the cached instance has been modified and based on whether the cache table entry indicates that the cached instance is a candidate for the deferred write back period.

Abstract translation: 这里描述的各种示例提供了基于年龄时间的延迟回写。 根据一些示例，监控存储在数据高速缓存上的高速缓存实例的老化时间，并且基于老化时间，可以修改高速缓存实例的高速缓存表项目以指示高速缓存实例是推迟的候选 回写期。 控制器可以基于数据高速缓存的数据活动来监视延迟回写期。 在延迟回写期间，基于高速缓存表条目是否指示高速缓存实例已被修改并且基于高速缓存表条目是否指示高速缓存实例可以将高速缓存实例从易失性存储器写回到非易失性存储器 实例是延迟回写期的候选人。

公开(公告)号：WO2016060737A1

公开(公告)日：2016-04-21

申请号：PCT/US2015/046097

申请日：2015-08-20

Applicant: QUALCOMM INCORPORATED

Inventor： CHRISTODORESCU, Mihai ,  SALAJEGHEH, Mastooreh ,  SUAREZ GRACIA, Dario

IPC: G06F11/34 ,  G06F11/30

CPC classification number: G06F3/0604 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/3003 ,  G06F11/3037 ,  G06F11/3471 ,  G06F21/56 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/885 ,  G06F2221/034

Abstract: Aspects include computing devices, systems, and methods for implementing monitoring communications between components and a memory hierarchy of a computing device. The computing device may determine at least one identifying factor for identifying execution of the processor-executable code. A communication between the components and the memory hierarchy of the computing device may be monitored for at least one communication factor of a same type as the at least one identifying factor. A determination whether a value of the at least one identifying factor matches a value of the at least one communication factor may be made. The computing device may determine that the processor-executable code is executed in response to determining that the value of the at least one identifying factor matches the value of the at least one communication factor.

Abstract translation: 方面包括用于实现组件之间的监视通信和计算设备的存储器层次结构的计算设备，系统和方法。 计算设备可以确定用于识别处理器可执行代码的执行的至少一个识别因素。 可以针对与至少一个识别因素相同类型的至少一个通信因素来监视计算设备的组件和存储器层次之间的通信。 可以进行至少一个识别因素的值是否与至少一个通信因素的值相匹配的确定。 响应于确定至少一个识别因子的值与至少一个通信因子的值相匹配，计算设备可以确定执行处理器可执行代码。

公开(公告)号：WO2015138375A3

公开(公告)日：2015-11-05

申请号：PCT/US2015019574

申请日：2015-03-10

Applicant: AMAZON TECH INC

Inventor： WEI DANNY ,  GUTHRIE II JOHN LUTHER ,  THOMPSON JAMES MICHAEL ,  HAWKS BENJAMIN ARTHUR ,  KUSTERS NORBERT P

IPC: G06F15/16

CPC classification number: G06F12/0866 ,  G06F11/1471 ,  G06F11/3409 ,  G06F11/3485 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/313 ,  G06F2212/461

Abstract: A block-based storage system may implement page cache write logging. Write requests for a data volume maintained at a storage node may be received at a storage node. A page cache for may be updated in accordance with the request. A log record describing the page cache update may be stored in a page cache write log maintained in a persistent storage device. Once the write request is performed in the page cache and recorded in a log record in the page cache write log, the write request may be acknowledged. Upon recovery from a system failure where data in the page cache is lost, log records in the page cache write log may be replayed to restore to the page cache a state of the page cache prior to the system failure.

Abstract translation: 基于块的存储系统可以实现页面缓存写入日志。 可以在存储节点处接收对存储节点处维护的数据卷的写入请求。 根据请求可以更新页面缓存。 描述页面高速缓存更新的日志记录可以存储在永久存储设备中维护的页面高速缓存写入日志中。 一旦写入请求在页面缓存中执行并记录在页面缓存写入日志中的日志记录中，写入请求可能会被确认。 从页缓存中的数据丢失的系统故障中恢复时，可能会重播页缓存写日志中的日志记录，以在系统故障之前将页缓存的状态恢复到页缓存。