中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

23 records (took 0.028 seconds)

    A NETWORKING INFRASTRUCTURE CENTER
    1.
    发明申请
    A NETWORKING INFRASTRUCTURE CENTER 审中-公开
    网络基础设施中心

    公开(公告)号：WO2017023247A1

    公开(公告)日：2017-02-09

    申请号：PCT/US2015/043131

    申请日：2015-07-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： RAYMOND, Patrick A. ,  SABOTTA, Michael L. ,  BENEDICT, Melvin K. ,  WANG, Han

    IPC: H04L12/931 ,  H04L29/04

    CPC classification number: H04L29/04 ,  H04L49/10 ,  H04L49/15 ,  H04L49/356 ,  H04L49/65

    Abstract: A networking infrastructure center includes a networking chassis, networking switches implemented in the networking chassis via module slots, the networking switches being swappable in the module slots to create an infrastructure topology, storage switches implemented in the networking chassis via the module slots, the storage switches being swappable to create the infrastructure topology, and a shuffler, the shuffler to detect locations of the networking switches and the storage switches to allow the networking switches and the storage switches to be placed in arbitrary locations on the networking chassis and to realize the infrastructure topology by splitting the infrastructure topology via physical signal multiplexing to physically isolate the networking switches and the storage switches.

    Abstract translation: 网络基础设施中心包括网络机箱，通过模块插槽在网络机箱中实现的网络交换机，网络交换机可在模块插槽中交换以创建基础架构拓扑，通过模块插槽实现在网络机箱中的存储交换机，存储交换机 可交换以创建基础架构拓扑，以及一个洗牌器，该洗牌器检测网络交换机和存储交换机的位置，以允许网络交换机和存储交换机放置在网络机箱上的任意位置，并实现基础架构拓扑 通过物理信号复用将基础架构拓扑分解，以物理隔离网络交换机和存储交换机。

    SCRUBBING DATA IN A MEMORY DEVICE
    4.
    发明申请
    SCRUBBING DATA IN A MEMORY DEVICE 审中-公开
    在存储设备中擦洗数据

    公开(公告)号：WO2017065802A1

    公开(公告)日：2017-04-20

    申请号：PCT/US2015/055976

    申请日：2015-10-16

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： BACCHUS, Reza M. ,  BENEDICT, Melvin K. ,  POPE, Eric L.

    IPC: G11C11/406 ,  G06F11/10

    CPC classification number: G06F11/106 ,  G11C7/04 ,  G11C11/4076

    Abstract: A memory device includes storage locations to store data, and an internal controller to perform scrubbing of a portion of the data stored by at least one storage location of the storage locations. The memory device also includes an interface to communicate non-deterministically over a communication bus with a memory controller.

    Abstract translation: 存储器设备包括存储位置以存储数据，以及内部控制器执行对存储位置的至少一个存储位置存储的数据的一部分的擦除。 存储设备还包括通过通信总线与存储控制器进行非确定性通信的接口。

    CORRECTING ERRORS OF A VARIABLE DATA PAYLOAD
    5.
    发明申请
    CORRECTING ERRORS OF A VARIABLE DATA PAYLOAD 审中-公开
    更正数据丢失的错误

    公开(公告)号：WO2016122463A1

    公开(公告)日：2016-08-04

    申请号：PCT/US2015/013124

    申请日：2015-01-27

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： WARNES, Lidia ,  BENEDICT, Melvin K.

    IPC: G06F11/10 ,  G06F12/00

    CPC classification number: G06F11/1004 ,  G06F12/0868 ,  G06F2212/1052 ,  G06F2212/214 ,  G06F2212/313

    Abstract: Correcting errors of a variable data payload includes receiving a data payload command to transfer a variable data payload from a memory controller to a memory device, determining, based on a size of the variable data payload, a number of cache lines for the variable data payload, assigning the variable data payload to the number of cache lines, transferring each of the cache lines with a cyclic redundancy check (CRC) character from the memory controller to the memory device to create a transfer, and validating, based on the CRC character, each of the cache lines of the transfer.

    Abstract translation: 可变数据有效负载的校正错误包括接收数据有效载荷命令以将可变数据有效载荷从存储器控制器传送到存储器设备，基于可变数据有效负载的大小确定用于可变数据有效载荷的高速缓存行的数量 将可变数据有效载荷分配给高速缓存行数，将具有循环冗余校验（CRC）字符的每个高速缓存行从存储器控制器传送到存储器设备以创建传输，并且基于CRC字符验证， 每个缓存行的传输。

    MEMORY CONTROLLER WITH MEMORY RESOURCE MEMORY MANAGEMENT
    6.
    发明申请
    MEMORY CONTROLLER WITH MEMORY RESOURCE MEMORY MANAGEMENT 审中-公开
    具有记忆资源记忆管理的记忆控制器

    公开(公告)号：WO2016085463A1

    公开(公告)日：2016-06-02

    申请号：PCT/US2014/067274

    申请日：2014-11-25

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： WRIGHT, Mitchel E. ,  KRAUSE, Michael R. ,  BENEDICT, Melvin K. ,  BARRON, Dwight L.

    IPC: G06F12/00

    CPC classification number: G06F12/023 ,  G06F11/20 ,  G06F12/0292 ,  G06F13/28 ,  G06T11/60 ,  G11C16/10

    Abstract: In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.

    Abstract translation: 在根据本公开的方面的示例实现中，公开了一种存储器控制器。 存储器控制器可通信地耦合到具有多个存储器资源区域的存储器资源，存储器资源区域可以与多个计算资源相关联。 存储器控制器可以包括将存储器控制器通信地耦合到存储器资源的存储器资源接口和用于将存储器控制器通信地耦合到多个计算资源的计算资源接口。 存储器控制器还可以包括用于管理存储器资源的存储器资源存储器管理单元。

    DEFERRED WRITE BACK BASED ON AGE TIME
    7.
    发明申请
    DEFERRED WRITE BACK BASED ON AGE TIME 审中-公开
    基于年龄时间的延迟回写

    公开(公告)号：WO2017142562A1

    公开(公告)日：2017-08-24

    申请号：PCT/US2016/018759

    申请日：2016-02-19

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： BENEDICT, Melvin K.

    IPC: G06F11/30 ,  G06F12/08

    CPC classification number: G06F11/30 ,  G06F11/3037 ,  G06F11/3423 ,  G06F12/08 ,  G06F2201/885

    Abstract: Various examples described herein provide for deferred write back based on age time. According to some examples, an age time for a cached instance stored on a data cache is monitored and, based on the age time, a cache table entry for the cached instance may be modified to indicate that the cached instance is a candidate for a deferred write back period. A controller may monitor for a deferred write back period based on data activity of the data cache. During a deferred write back period, the cached instance may be written back from volatile memory to the non-volatile memory based on whether the cache table entry indicates that the cached instance has been modified and based on whether the cache table entry indicates that the cached instance is a candidate for the deferred write back period.

    Abstract translation: 这里描述的各种示例提供了基于年龄时间的延迟回写。 根据一些示例，监控存储在数据高速缓存上的高速缓存实例的老化时间，并且基于老化时间，可以修改高速缓存实例的高速缓存表项目以指示高速缓存实例是推迟的候选 回写期。 控制器可以基于数据高速缓存的数据活动来监视延迟回写期。 在延迟回写期间，基于高速缓存表条目是否指示高速缓存实例已被修改并且基于高速缓存表条目是否指示高速缓存实例可以将高速缓存实例从易失性存储器写回到非易失性存储器 实例是延迟回写期的候选人。

    EXPANSION BUS DEVICES
    8.
    发明申请
    EXPANSION BUS DEVICES 审中-公开
    扩展总线设备

    公开(公告)号：WO2017069777A1

    公开(公告)日：2017-04-27

    申请号：PCT/US2015/057178

    申请日：2015-10-23

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： BENEDICT, Melvin K. ,  PURCELL, Brian T.

    IPC: G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/4022

    Abstract: The present disclosure discloses an expansion bus device for a computing device. The computing device includes a plurality of host devices and a plurality of input-output devices. The expansion bus device is configured to communicatively connect the host devices and the input-output devices. The expansion bus device includes a plurality of host interface devices configured to be connected to the host devices of the computing device and a plurality of I/O slots configured to support the I/O devices of the computing device. The expansion bus device further includes a retimer switch configured to communicatively connect the host interface devices of the computing device and the I/O slots of the computing device, thereby communicatively connecting the host devices supported by the host interface devices to the I/O devices disposed within the I/O slots.

    Abstract translation: 本公开公开了一种用于计算设备的扩展总线设备。 该计算设备包括多个主机设备和多个输入输出设备。 扩展总线设备被配置为可通信地连接主机设备和输入输出设备。 扩展总线设备包括被配置为连接到计算设备的主机设备的多个主机接口设备以及被配置为支持计算设备的I / O设备的多个I / O槽。 扩展总线设备还包括重定时器开关，该重定时器开关被配置为通信地连接计算设备的主机接口设备和计算设备的I / O插槽，从而将主机接口设备所支持的主机设备通信地连接到I / O设备 置于I / O插槽内。

    PHYSICAL MEMORY REGION BACKUP OF A VOLATILE MEMORY TO A NON-VOLATILE MEMORY
    9.
    发明申请
    PHYSICAL MEMORY REGION BACKUP OF A VOLATILE MEMORY TO A NON-VOLATILE MEMORY 审中-公开
    易失性存储器的物理存储区域备份到非易失性存储器

    公开(公告)号：WO2017039598A1

    公开(公告)日：2017-03-09

    申请号：PCT/US2015/047660

    申请日：2015-08-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： BENEDICT, Melvin K. ,  POPE, Eric L.

    IPC: G06F12/16 ,  G06F11/14

    CPC classification number: G06F11/14 ,  G06F11/1441 ,  G06F12/16

    Abstract: In one example in accordance with the present disclosure, a system for backup of a physical memory region of volatile memory. The system may include: a non-volatile memory, a volatile memory, at least one processor to: execute an application that indicates a virtual memory region stored in the volatile memory, wherein the virtual memory region is associated with an application, determine a corresponding physical memory region of the volatile memory for backup based on the indicated virtual memory region, and at least one memory controller to: receive a backup signal for the physical memory region of the volatile memory, and responsive to receiving the backup signal, backup up the physical memory region of the volatile memory to a memory region of the non-volatile memory.

    Abstract translation: 在根据本公开的一个示例中，用于备份易失性存储器的物理存储器区域的系统。 所述系统可以包括：非易失性存储器，易失性存储器，至少一个处理器，用于：执行指示存储在所述易失性存储器中的虚拟存储器区域的应用，其中所述虚拟存储器区域与应用相关联， 用于基于所指示的虚拟存储器区域进行备份的易失性存储器的物理存储器区域，以及至少一个存储器控制器，用于：接收用于易失性存储器的物理存储器区域的备份信号，并且响应于接收备份信号，备份 易失性存储器的物理存储器区域到非易失性存储器的存储器区域。

    VALIDATING DATA IN A STORAGE ARRAY
    10.
    发明申请
    VALIDATING DATA IN A STORAGE ARRAY 审中-公开
    在存储阵列中验证数据

    公开(公告)号：WO2016122655A1

    公开(公告)日：2016-08-04

    申请号：PCT/US2015/013954

    申请日：2015-01-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： BENEDICT, Melvin K. ,  WARNES, Lidia ,  SCHOELLER, Patrick M.

    IPC: G11C29/42

    CPC classification number: G06F11/1004

    Abstract: Validating data in a storage array includes receiving, from a memory controller, a write command to write data to a storage array of a storage element, transferring the data with a cyclic redundancy check (CRC) character to the storage element to create a transfer, writing, based on the transfer, the data with the CRC character to the storage array of the storage element to create written data and a written CRC character, and validating, via a sense amplifier, the written data.

    Abstract translation: 验证存储阵列中的数据包括从存储器控制器接收写入命令以将数据写入存储元件的存储阵列，将具有循环冗余校验（CRC）字符的数据传送到存储元件以创建传输， 基于传送将具有CRC字符的数据写入存储元件的存储阵列以创建写入数据和写入的CRC字符，并通过读出放大器验证写入的数据。

Patent Agency Ranking