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公开(公告)号：US20190272210A1
公开(公告)日：2019-09-05
申请号：US16289405
申请日：2019-02-28
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
IPC: G06F11/07
Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.
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公开(公告)号：US20190258493A1
公开(公告)日：2019-08-22
申请号：US16273704
申请日：2019-02-12
Inventor： Roberto Colombo , Om RANJAN
Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration data client.
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公开(公告)号：US20190227747A1
公开(公告)日：2019-07-25
申请号：US16249524
申请日：2019-01-16
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
IPC: G06F3/06
Abstract: A processing system includes a plurality of configuration data clients, each of the plurality of configuration data clients having a register and being associated with a respective address. The system includes a non-volatile memory with configuration data for each of the plurality of configuration data clients. The configuration data is stored as data packets having an attribute field identifying the respective address of the plurality of configuration data clients and the respective configuration data. A hardware configuration circuit is configured to sequentially read the data packets from the non-volatile memory and transmit the respective configuration data read from the non-volatile memory to the respective configuration data client. The configuration data client is configured to receive a first set of configuration data addressed to the respective address from the hardware configuration circuit and store the first set of configuration data in the respective register. The configuration data client is configured to receive a second set of configuration data addressed to the respective address from the hardware configuration circuit, and verify whether further configuration data may be written to the respective register as a function of a type identification signal. In response to verifying that further configuration data may be written to the respective register, the configuration data client is configured to overwrite the first set of configuration data by storing the second set of configuration data in the respective register. In response to verifying that further configuration data may not be written to the respective register, the configuration data client is configured to maintain the first set of configuration data by inhibiting storage of the second set of configuration data received in the respective register.
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公开(公告)号：US20190026498A1
公开(公告)日：2019-01-24
申请号：US16039103
申请日：2018-07-18
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
Abstract: In an embodiment, a processing system includes a non-volatile memory, a hardware block, a protection circuit associated with the hardware block, and a password verification circuit. The non-volatile memory stores at least one reference password. The password verification circuit is configured to receive a password verification command, obtain a reference password, and test whether the passwords correspond. In case the passwords correspond, the password verification circuit generate an overwrite signal. The protection circuit is configured to receive a control command and selectively forward the control command to the associated hardware block as a function of the overwrite signal.
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公开(公告)号：US20180357015A1
公开(公告)日：2018-12-13
申请号：US15991208
申请日：2018-05-29
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
CPC classification number: G06F3/0679 , G05B19/056 , G06F12/0246 , G06F13/38 , G06F21/76
Abstract: A processing system includes a processing unit and a hardware block configured to change operation as a function of life cycle data. A one-time programmable memory includes original life cycle data. A hardware configuration module is configured to read the original life cycle data from the one-time programmable memory and provide the original life cycle data to the hardware block. The hardware configuration module includes a register providing the life cycle data used to change operation of the hardware block. The hardware configuration module is configured to store the original life cycle data in the register and receive a command from the processing unit. The command includes a write request for storing new life cycle data in the register.
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Patent Agency Ranking
公开(公告)号：US09793960B2
公开(公告)日：2017-10-17
申请号：US13944169
申请日：2013-07-17
Inventor： Juergen Boehler , Alexandre Charles
CPC classification number: H04B5/0056 , H04L63/0492 , H04M1/7253 , H04M2250/04 , H04W4/80 , H04W12/02
Abstract: An NFC device may include a first and second controller interfaces, a first communication channel coupled to the first controller interface, and a second communication channel connected to the second controller interface. A secure element may include a secure element interface connected to the first communication channel and encryption/decryption circuitry configured to encrypt data to be sent on the first communication channel for being framed into the encrypted frames and to decrypt encrypted data extracted from the encrypted frames and received from the first communication channel. The secure element may also include management circuitry configured to control the encryption/decryption circuitry for managing the encrypted communication with the NFC controller. A device host may include a host device interface coupled to the second controller interface and control means or circuitry configured to control the management circuitry through non-encrypted commands exchanged on the first and second communication channels.
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167.发明授权Active battery balancing circuit and method of balancing an electric charge in a plurality of cells of a battery 有权有源电池平衡电路和平衡电池多个电池中的电荷的方法公开(公告)号：US09496724B2
公开(公告)日：2016-11-15
申请号：US13849374
申请日：2013-03-22
Applicant: STMicroelectronics Application GmbH
Inventor： Reiner Schwartz
CPC classification number: H02J7/0019 , B60L11/1866 , B60L2240/547 , B60L2240/549 , H02J7/0016 , Y02T10/7005 , Y02T10/7061
Abstract: A method and an active battery balancing circuit for balancing an electric charge in a plurality of cells of a battery that are electrically connected in series is disclosed. A first subset of the cells of the battery is electrically connected to an inductance for providing a current flow from the first subset through the inductance. The first subset of the cells is disconnected from the inductance, and a current is allowed to flow from the inductance into a second subset of the cells of the battery. At least one of the first and the second subset of the cells of the battery comprises two or more cells.
Abstract translation: 公开了一种用于平衡串联电连接的电池的多个单电池中的电荷的方法和有源电池平衡电路。 电池的单元的第一子集电连接到电感，以提供来自第一子集的电流流过电感。 电池的第一子集与电感断开，并且允许电流从电感流入电池单元的第二子集。 电池单元的第一和第二子集中的至少一个包括两个或更多个单元。
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公开(公告)号：EP4373038A1
公开(公告)日：2024-05-22
申请号：EP23207659.6
申请日：2023-11-03
Inventor： DONDINI, Mirko , TRECARICHI, Calogero Andrea , RENNIG, Fred
IPC: H04L12/40
CPC classification number: H04L12/40006 , H04L2012/4021520130101 , H04L2012/4027320130101
Abstract: A processing system (10a) is described. The processing system (10a) comprises a processing circuit (64), a volatile memory (60a) and a CAN communication controller circuit (50). The CAN communication controller circuit (50) comprises configuration and status registers (520). A transmission handler circuit (502) and a reception handler circuit (504) are configured to transmit and receive data via the CAN core circuit (500) by exchanging data with the volatile memory (60a) based on the configuration data stored to the configuration and status registers (520), and standard and/or extended filter elements stored to the volatile memory (60a).
Specifically, the processing system (10a) further comprises a hardware host circuit (62a) comprising a non-volatile memory (642) configured to store first configuration data (CD1) and second configuration data (CD2), wherein the first configuration data (CD1) comprise configuration data to be transferred to the configuration and status registers (520) of the CAN communication controller circuit (50) and the second configuration data (CD2) comprise at least one standard and/or extended filter element to be transferred to the volatile memory (60a). A control circuit (620, 628, 632) is configured to manage an initialization mode, a reception mode and a transmission mode. Specifically, during the initialization mode (648), the hardware host circuit (62a) stores the first configuration data (CD1) to the configuration and status registers (520) and the second configuration data (CD2) to the volatile memory (60a).-
169.发明公开
公开(公告)号：EP4319064A1
公开(公告)日：2024-02-07
申请号：EP23185507.3
申请日：2023-07-14
Applicant: STMicroelectronics Application GmbH
Inventor： RENNIG, Fred
IPC: H04L12/40 , H04L61/5038 , H04L41/08
Abstract: An electronic device (42) includes a CAN protocol controller (320), a first communication port (326d) configured for coupling to a first segment of a differential bus to exchange CAN signals therewith, and a second communication port (326u) configured for coupling to a second segment of the differential bus to exchange CAN signals therewith. A first CAN transceiver circuit (324d) is coupled to the CAN protocol controller (320) and is configured to receive a first CAN transmission signal ( TXDd ) therefrom and to transmit a first CAN reception signal ( RXDd ) thereto. The first CAN transceiver circuit (324d) is coupled to the first communication port (326d) to drive (50) a differential voltage at the first segment of the differential bus as a function of the first CAN transmission signal ( TXDd ) and to sense (56) a differential voltage at the first segment of the differential bus to produce the first CAN reception signal ( RXDd ) . The second communication port (326u) is enabled in response to a control signal ( DISABLE ) being de-asserted and disabled in response to the control signal ( DISABLE ) being asserted. The CAN signals are passed between the first communication port (326d) and the second communication port (326u) in response to the control signal ( DISABLE ) being de-asserted, and the CAN signals are not passed between the first communication port (326d) and the second communication port (326u) in response to the control signal ( DISABLE ) being asserted.
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公开(公告)号：EP4174692A1
公开(公告)日：2023-05-03
申请号：EP22201273.4
申请日：2022-10-13
Inventor： GOYAL, Avneep Kumar , SZURMANT, Thomas
Abstract: A system on a chip including a first-port controller (106) for a first development port (102) configured to receive a first development tool and a second-port controller (108) for a second development port (104) configured to receive a second development tool. The system on a chip further including a central controller (110) in communication with the first-port controller (106), the second-port controller (108), and a security subsystem (112). The central controller (110) being configured to manage authentication exchanges between the security subsystem (112) and the first development tool and authentication exchanges between the security subsystem (112) and the second development tool.
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