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公开(公告)号：EP4376388A1
公开(公告)日：2024-05-29
申请号：EP23306929.3
申请日：2023-11-09
Applicant: STMicroelectronics (ALPS) SAS , STMicroelectronics Application GmbH , STMicroelectronics S.r.l.
Inventor： RENNIG, Fred , TORRISI, Giovanni Luca , GAERTNER, Manuel , SIRITO-OLIVIER, Philippe , BURKHARDT, Fritz , OCCHIPINTI, Aldo
CPC classification number: H04L2012/4021520130101 , H04L2012/4027320130101 , B60R16/023 , H04L12/12 , H04L12/40039
Abstract: In a vehicle communication network, a plurality of electronic control units (44'), ECUs, are arranged in groups. The ECUs pertaining to a same group are coupled to each other via a respective dedicated communication bus (59) operated according to a CAN protocol. A respective local controller (40') including a microcontroller unit (50) is coupled to each group of ECUs (44') via the respective dedicated communication bus (59) to exchange CAN frames therewith. A central controller is coupled to the local controllers (40') via a vehicle communication bus. Electrical loads (402-406) are coupled to the ECUs (44') to receive actuation signals therefrom and/or provide feedback signals thereto. Each microcontroller unit (50) of the local controllers (40') is configured as communication commander device to transmit and receive CAN frames via the respective dedicated communication bus (59). Each of the ECUs (44') includes a respective logic circuit (48') configured as communication responder device. In response to a CAN frame being received from the respective local controller (40'), the logic circuit (48') decodes the received CAN frame to produce the actuation signal for a respective electrical load (402-406). In response to a feedback signal being received from the respective electrical load (402-406), the logic circuit (48') transmits a CAN wake-up frame to the respective local controller (40') and encodes the feedback signal into a CAN frame for transmission to the respective local controller (40').
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公开(公告)号：EP4373038A1
公开(公告)日：2024-05-22
申请号：EP23207659.6
申请日：2023-11-03
Inventor： DONDINI, Mirko , TRECARICHI, Calogero Andrea , RENNIG, Fred
IPC: H04L12/40
CPC classification number: H04L12/40006 , H04L2012/4021520130101 , H04L2012/4027320130101
Abstract: A processing system (10a) is described. The processing system (10a) comprises a processing circuit (64), a volatile memory (60a) and a CAN communication controller circuit (50). The CAN communication controller circuit (50) comprises configuration and status registers (520). A transmission handler circuit (502) and a reception handler circuit (504) are configured to transmit and receive data via the CAN core circuit (500) by exchanging data with the volatile memory (60a) based on the configuration data stored to the configuration and status registers (520), and standard and/or extended filter elements stored to the volatile memory (60a).
Specifically, the processing system (10a) further comprises a hardware host circuit (62a) comprising a non-volatile memory (642) configured to store first configuration data (CD1) and second configuration data (CD2), wherein the first configuration data (CD1) comprise configuration data to be transferred to the configuration and status registers (520) of the CAN communication controller circuit (50) and the second configuration data (CD2) comprise at least one standard and/or extended filter element to be transferred to the volatile memory (60a). A control circuit (620, 628, 632) is configured to manage an initialization mode, a reception mode and a transmission mode. Specifically, during the initialization mode (648), the hardware host circuit (62a) stores the first configuration data (CD1) to the configuration and status registers (520) and the second configuration data (CD2) to the volatile memory (60a).-
公开(公告)号：EP4105785A1
公开(公告)日：2022-12-21
申请号：EP22176130.7
申请日：2022-05-30
Inventor： CAVALLARO, Giuseppe , RENNIG, Fred
Abstract: A microcontroller (80) comprises a processing unit and a deserial-serial peripheral interface module (81'). The deserial-serial peripheral interface module is configured to be coupled to a communication bus (84) which operates according to a selected communication protocol. The processing unit is configured to read user data intended for inclusion in an outgoing frame encoded according to the selected communication protocol. The processing unit is further configured to calculate, as a function of the user data, a CRC value intended for inclusion in the outgoing frame. The processing unit is further configured to compose the outgoing frame including the user data and the calculated CRC value into the outgoing frame. The processing unit is further configured to produce a DSPI frame encoded according to the selected communication protocol as a function of the outgoing frame. The processing unit is further configured to program a data register of the deserial-serial peripheral interface module (81') with the DSPI frame. Operation of the deserial-serial peripheral interface module (81') results in transmission of the DSPI frame via the communication bus (84).
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公开(公告)号：EP4246900A1
公开(公告)日：2023-09-20
申请号：EP23158838.5
申请日：2023-02-27
Applicant: STMicroelectronics Application GmbH , STMicroelectronics Design and Application s.r.o. , STMicroelectronics S.r.l.
Inventor： RENNIG, Fred , BARTHEL, Jochen , BERAN, Ludek , DONDINI, Mirko , DVORAK, Vaclav , POLISI, Vincenzo , SANZA', Marianna , TRECARICHI, Calogero Andrea , FURIO, Alfonso
Abstract: A processing system (10a) is described. The processing system comprises a three-state driver circuit (502) and a CAN FD Light controller (500). The CAN FD Light controller (500) is configured to sequentially transmit the bits of a CAN FD Light frame, wherein the CAN FD Light frame comprises a start-of-frame bit (SOF), a sequence of bits (CD-EOF) comprising in sequence a Cyclic Redundancy Check, CRC, delimiter bit (CD), an acknowledge bit (AS), an acknowledge delimiter bit (AD) and an End-of-Frame field (EOF) having 7 bits, and a plurality of intermediate bits (SID-CRC) between said start-of-frame bit (SOF) and said CRC delimiter bit (CD).
In particular, the CAN FD Light controller (500) is configured to sequentially transmit the bits of the CAN FD Light frame via the three-state driver circuit (502) by using a push-pull configuration (CTRL1) when transmitting the start-of-frame bit (SOF) and the intermediate bits (SID-CRC). However, once having transmitted the intermediate bits (SID-CRC), the CAN FD Light controller (500) activates a high-impedance state (CTRL1) of the three-state driver circuit (502).-
公开(公告)号：EP4138343A1
公开(公告)日：2023-02-22
申请号：EP22188198.0
申请日：2022-08-02
Inventor： RENNIG, Fred , DVORAK, Vaclav
IPC: H04L12/40
Abstract: A processing system (10a) is described. The processing system (10a) comprises a transmission terminal (TX) configured to provide a transmission signal (TXD), a reception terminal (RX) configured to receive a reception signal (RXD), a microprocessor (1020) programmable via software instructions, a memory controller (100) configured to be connected to a memory (104, 104b), a serial communication interface (50), and a communication system (114).
Specifically, the serial communication interface (50) supports a CAN FD Light mode of operation and a UART mode of operation. For this purpose, the serial communication interface (50) comprises a control register (CTRL), a clock management circuit (5044), a transmission shift register (5040; 5056), a transmission control circuit (5046), a reception shift register (5042; 5056) and a reception control circuit (5048).
Accordingly, the microprocessor (1020) may transmit and/or receive CAN FD Light or UART frames via the same serial communication interface (50).-
Patent Agency Ranking
公开(公告)号：EP4137954A1
公开(公告)日：2023-02-22
申请号：EP22188131.1
申请日：2022-08-01
Inventor： DVORAK, Vaclav , RENNIG, Fred
Abstract: A processing system (10a) is described. The processing system comprises a Serial Peripheral Interface, SPI, communication interface (50), a microprocessor (1020), a memory controller (100) connected to a memory (104, 104b), and two DMA channels (DMA 1 , DMA 2 ) configured to transfer packets between the SPI interface (50) and the memory (104b). In particular, the processing system comprises an edge detector (600, 620) configured to assert a first control signal (IRQ 60 ) in response to a falling edge in the reception signal (RXD), a first hardware timer circuit (60) configure to, when enabled, generate a clock signal (PWM) for the SPI communication interface (50) and a second hardware timer circuit (62) configure to, when enabled, increase a count value and assert a second control signal (IRQ 62 ) in response to determining that the count value reaches a given threshold value.
Specifically, the processing system (10a) is configured to manage a CAN FD Light data transmission mode and/or CAN FD Light data reception mode by using the SPI communication interface. For example, in the CAN FD Light data reception mode, the microprocessor (1020) activates a slave mode of the SPI communication interface (50), enables the first hardware timer circuit (60) and the second hardware timer circuit (62) in response to the first control signal (IRQ 60 ), whereby the second DMA channel (DMA 2 ) transfers packets from the SPI communication interface (50) to the memory (104b), thereby sequentially transferring a reception CAN FD Light frame from the SPI communication interface (50) to the memory (104b), and reads the reception CAN FD Light frame from the memory (104b) in response to the second control signal (IRQ 62 ).-
公开(公告)号：EP4057574A1
公开(公告)日：2022-09-14
申请号：EP22157917.0
申请日：2022-02-22
Inventor： RENNIG, Fred , DVORAK, Vaclav
Abstract: A circuit (106) comprises a first (24a) and a second (24b) memory, a processing unit (21) and a timer (22). The processing unit generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. Each PWM period has a dominant portion and a recessive portion, and a total duration. The processing unit stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory, wherein the first and second parameter define a shape of the PWM periods. The timer comprises a first register (220) which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter (221) which increases a count number and resets the count number as a function of the value of the first register. A value of the first parameter of a subsequent PWM period is stored into the first register as a function of the value of the first register. The timer comprises a second register (222) which reads from the second memory a value of the second parameter of the current PWM period, and compares the count number of the counter circuit to such value. The second register drives an output pin (230) to a dominant (resp., recessive) value as a function of said comparing the count number of the counter circuit to the value of the second register. A value of the second parameter of a subsequent PWM period is stored into the second register in response to the count number reaching the value stored in the first or second register.
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公开(公告)号：EP4012984A1
公开(公告)日：2022-06-15
申请号：EP21212062.0
申请日：2021-12-02
Applicant: STMicroelectronics Application GmbH
Inventor： RENNIG, Fred , NANDLINGER, Rolf
IPC: H04L12/40
Abstract: A processing system is described. The processing system comprises a first CAN XL communication system (50 1 ) and a second CAN XL communication system (50 2 ), wherein each CAN XL communication system (50 1 , 50 2 ) comprises a CAN XL protocol controller configured to generate a NRZ encoded transmission signal (TXD) and receive a NRZ encoded reception signal (RXD). Each CAN XL communication system (50 1 , 50 2 ) is configured to generate a first transmission signal (TXD1) by selecting the NRZ encoded transmission signal (TXD) or a PWM signal generated as a function of the NRZ encoded transmission signal (TXD).
Specifically, the processing system (10a) comprises a bus (22) having a transmission node (TX2) and a reception node (RX2), wherein the bus (22) is configured to receive from each CAN XL communication system (50 1 , 50 2 ) a respective second transmission signal (TXD2) and drive the logic level at the transmission node (TX2) as a function of the logic levels of the second transmission signals (TXD2), and provide to each CAN XL communication system (50 1 , 50 2 ) a respective second reception signal (RXD2) having a logic level determined as a function of the logic level at the reception node (RX2). Moreover, the processing system comprises a switching circuit (24, 224, 306, 308, 52, 520) configured to support a plurality of modes, wherein, in a first mode, the switching circuit (24, 224, 306, 308, 52, 520) is configured to provide the NRZ encoded transmission signals (TXD) of the CAN XL communication systems (50 1 , 50 2 ) as the second transmission signals (TXD2) to the bus system (22), and provide the respective second reception signal (RXD2) received from the bus (22) to the CAN XL protocol controllers (300) of the CAN XL communication system (50 1 , 50 2 ).-
9.发明公开
公开(公告)号：EP4319064A1
公开(公告)日：2024-02-07
申请号：EP23185507.3
申请日：2023-07-14
Applicant: STMicroelectronics Application GmbH
Inventor： RENNIG, Fred
IPC: H04L12/40 , H04L61/5038 , H04L41/08
Abstract: An electronic device (42) includes a CAN protocol controller (320), a first communication port (326d) configured for coupling to a first segment of a differential bus to exchange CAN signals therewith, and a second communication port (326u) configured for coupling to a second segment of the differential bus to exchange CAN signals therewith. A first CAN transceiver circuit (324d) is coupled to the CAN protocol controller (320) and is configured to receive a first CAN transmission signal ( TXDd ) therefrom and to transmit a first CAN reception signal ( RXDd ) thereto. The first CAN transceiver circuit (324d) is coupled to the first communication port (326d) to drive (50) a differential voltage at the first segment of the differential bus as a function of the first CAN transmission signal ( TXDd ) and to sense (56) a differential voltage at the first segment of the differential bus to produce the first CAN reception signal ( RXDd ) . The second communication port (326u) is enabled in response to a control signal ( DISABLE ) being de-asserted and disabled in response to the control signal ( DISABLE ) being asserted. The CAN signals are passed between the first communication port (326d) and the second communication port (326u) in response to the control signal ( DISABLE ) being de-asserted, and the CAN signals are not passed between the first communication port (326d) and the second communication port (326u) in response to the control signal ( DISABLE ) being asserted.
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公开(公告)号：EP3913864A1
公开(公告)日：2021-11-24
申请号：EP21172208.7
申请日：2021-05-05
Inventor： RENNIG, Fred , DVORAK, Vaclav , BERAN, Ludek
IPC: H04L12/40
Abstract: A method of operating a CAN bus comprises coupling a first device (10) and second devices (20 1 , ..., 20 n ) to the CAN bus (30) via respective CAN transceiver circuits. The method comprises configuring the first device as a communication master device to transmit first messages carrying operation data message portions indicative of operations for implementation by the second devices, and second messages addressed to the second devices, the second messages conveying identifiers identifying respective ones of the second devices to which the second messages are addressed requesting respective reactions towards the first device within respective expected reaction intervals. The method comprises configuring the second devices as communication slave devices to receive the first messages transmitted from the first device, read respective operation data message portions in said operation data message portions and implement respective operations as a function of the respective operation data message portions read, and to receive the second messages transmitted from the first device and react thereon within said respective expected reaction intervals by transmitting reaction messages towards the first device. The method comprises configuring said respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of said messages via the CAN bus by the respective first device or second device.
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