公开(公告)号：US12056505B2

公开(公告)日：2024-08-06

申请号：US17862257

申请日：2022-07-11

Applicant: XILINX, INC.

Inventor： Ahmad R. Ansari ,  David P. Schultz

IPC: G06F15/177 ,  G06F9/00 ,  G06F9/24 ,  G06F9/445

CPC classification number: G06F9/44505

Abstract: Embodiments herein describe a distributed configuration system for a configurable device. Instead of relying solely on a central configuration manager to distribute configuration information to various subsystems in the device, the embodiments herein include configuration interface managers (CIM) that are distributed in different regions of the device, whether those regions are in one integrated circuit or include multiple integrated circuits. The embodiments can still use a central configuration manager to distribute configuration information in a device image to the plurality of CIMs, which can then forward the configuration information to their assigned regions.

公开(公告)号：US12047275B2

公开(公告)日：2024-07-23

申请号：US17705087

申请日：2022-03-25

Applicant: XILINX, INC.

Inventor： Aman Gupta ,  Jaideep Dastidar ,  Jeffrey Cuppett ,  Sagheer Ahmad

IPC: H04L45/24 ,  H04L45/74 ,  H04L49/109

CPC classification number: H04L45/24 ,  H04L45/74 ,  H04L49/109

Abstract: Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send first traffic, aggregated across the multiple physical channels, to the first destination and wherein the lower bandwidth client is configured to send second traffic, concurrently with sending the first traffic, from the lower bandwidth client, dispersed over two or more of the multiple physical channels, to the second destination.

公开(公告)号：US12045469B2

公开(公告)日：2024-07-23

申请号：US18082223

申请日：2022-12-15

Applicant: XILINX, INC.

Inventor： Kumar Rahul ,  John J. Wuu ,  Santosh Yachareni ,  Nui Chong ,  Cheang Whang Chang

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0673

Abstract: A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.

公开(公告)号：US20240224542A1

公开(公告)日：2024-07-04

申请号：US18090216

申请日：2022-12-28

Applicant: XILINX, INC.

Inventor： Zachary BLAIR ,  Gabriel LOH ,  Paul HARTKE

IPC: H10B80/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B80/00 ,  H01L23/5223 ,  H01L23/5286

Abstract: A DRAM fabrication process for producing a semiconductor die adapted for having the ability to be both a hybrid memory and power supply capacitance. DRAM arrays on a semiconductor die may be individually selected to function as either a memory or as supplemental capacitance on a power distribution network serving circuits on one or more semiconductor dice in a three-dimensional active-on-active (AoA) stacked semiconductor die package configuration. Defective DRAM array trench capacitors can be repurposed to serve as supplemental capacitance on a power distribution network. DRAM array trench capacitors can be dynamically reassigned as supplemental capacitance when power supply monitors sense that additional power supply capacitance is needed.

公开(公告)号：US20240220436A1

公开(公告)日：2024-07-04

申请号：US18148699

申请日：2022-12-30

Applicant: Xilinx, Inc.

Inventor： Martin Diaz ,  Carsten Hoffmann ,  Jerome Dale Wong

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4282

Abstract: A system includes a plurality of controller circuits. The system includes a plurality of target circuits. The system includes a communication bus communicatively linking the plurality of controller circuits with the plurality of target circuits. The communication bus includes a plurality of switches. Each switch of the plurality of switches is connected to a different one of the plurality of controller circuits.

公开(公告)号：US20240220365A1

公开(公告)日：2024-07-04

申请号：US18090207

申请日：2022-12-28

Applicant: XILINX, INC.

Inventor： Ramakrishna Ganeshu POOLLA ,  Bharath MULAGONDLA ,  Felix BURTON ,  Mohan Marutirao DHANAWADE

IPC: G06F11/14 ,  G06F9/4401

CPC classification number: G06F11/1417 ,  G06F9/4401 ,  G06F2201/805

Abstract: Error and debug information is saved during a boot process. A read only memory (ROM) debug circuitry (RDC) obtains detected errors within ROM code during a boot process. Error information is generated and stored within a first memory element. The error information includes entries. Each of the entries is associated with a respective one of the errors. Debug information is generated and stored by the RDC within a second memory element. The debug information is associated with the boot process. Further, the method includes outputting, via test circuitry of the processing system, the error information and debug information based on a testing instruction.

公开(公告)号：US12026444B2

公开(公告)日：2024-07-02

申请号：US17522834

申请日：2021-11-09

Applicant: Xilinx, Inc.

Inventor： Hao Yu ,  Jun Liu

IPC: G06F30/343 ,  G06F30/327 ,  G06F30/347

CPC classification number: G06F30/343 ,  G06F30/327 ,  G06F30/347

Abstract: Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).

公开(公告)号：US12019576B2

公开(公告)日：2024-06-25

申请号：US17879675

申请日：2022-08-02

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Ygal Arbel ,  Sagheer Ahmad ,  Abbas Morshed

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F2213/40

Abstract: Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.

公开(公告)号：US12019526B2

公开(公告)日：2024-06-25

申请号：US17746843

申请日：2022-05-17

Applicant: XILINX, INC.

Inventor： David Tran ,  Aditi R. Ganesan ,  Anurag Goyal

IPC: H03L7/081 ,  G06F11/16

CPC classification number: G06F11/1679 ,  H03L7/0814

Abstract: Methods and systems to detect a metastable condition and suppress/mask a signal during the metastable condition. The metastable condition may arise from asynchronous sampling. Techniques disclosed herein may be configured to enable asynchronous lock-stepping, where outputs of redundant circuit blocks of a first clock domain are received at input nodes of a second clock domain. In the second clock domain, logic states at the input nodes are compared to detect errors, and results of the comparison are masked during transitions at the input nodes. Masking may be constrained to situations where logic states at the input nodes differ.

公开(公告)号：US20240184736A1

公开(公告)日：2024-06-06

申请号：US18073327

申请日：2022-12-01

Applicant: XILINX, INC.

Inventor： David P. SCHULTZ ,  Richard W. SWANSON

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F2213/0016

Abstract: An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. A frequency of the interface clock signal is a multiple of a frequency of the logic clock signal.