公开(公告)号：KR1019970006607B1

公开(公告)日：1997-04-29

申请号：KR1019930027341

申请日：1993-12-11

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 오광룡 ,  한덕영 ,  김홍만

IPC: H01L31/08 ,  H01L31/10

Abstract: A method for fabricating an optical switch is described that provides a structure which can improve the operation speed of the optical switch. The method includes the steps of forming an n--InGaAs light guiding path layer 2 and n--InP layer 3, selectively removing the n--InP layer 3 and light guiding path layer 2, forming an n+-InGaAs light guiding path layer 4, an n--InP clad layer 5, n--InP blocking layer 6, n--InGaAs capping layer 7 and p--InGaAs capping layer 8 in sequence, selectively etching the parts which refect the light, diffusing Zn at the parts, selectively etching the p--InGaAs capping layer 8, n--InGaAs capping layer 7, n--InP blocking layer 6 and n--InP clad layer 5, depositing a SiNx insulating layer 9, and selectively etching the insulating layer 9, forming a p-type electrode 11 prior to deposition of an n-type electrode. Thereby, it is possible to improve the operation speed of the optical switch and thus increase the amount of data exchanged.

Abstract translation: 描述了一种用于制造光开关的方法，其提供了可以提高光开关的操作速度的结构。 该方法包括以下步骤：形成n-InGaAs导光路径层2和n-InP层3，选择性地去除n-InP层3和导光路径层2，形成n + -InGaAs光导路径层 如图4所示，n-InP包层5，n-InP阻挡层6，n-InGaAs覆盖层7和p-InGaAs覆盖层8依次，选择性地蚀刻反射光的部分，在 选择性蚀刻p-InGaAs覆盖层8，n-InGaAs覆盖层7，n-InP阻挡层6和n-InP覆盖层5，沉积SiNx绝缘层9，并且选择性地蚀刻绝缘层 如图9所示，在n型电极沉积之前形成p型电极11。 由此，能够提高光开关的动作速度，能够增加数据交换量。

公开(公告)号：KR1019970004489B1

公开(公告)日：1997-03-28

申请号：KR1019930018146

申请日：1993-09-09

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 박기성 ,  오광룡 ,  박종대 ,  김홍만

IPC: H01L29/86 ,  H01L29/8605

CPC classification number: Y02E10/50

Abstract: This invention is about a manufacturing method of an internal total reflection type semiconductor optical switch using refraction ratio change of an optical wave guide by injection current. The method includes the steps of: raising an InGaAsP optical wave guide layer(2) not doped by epitaxy method and an InP clad layer(3) by order on the 1st-type InP substrate(1); etching a certain region of the clad layer(3) on which an optical detector is to be formed; forming the 2nd-type diffusion region by raising an InGaAsP cap layer(4) not doped by epitaxy method and diffusing dopant on a certain region of the cap layer(4); forming a pn junction of an optical switch and an optical detector and forming an optical wave guide by etching the cap layer(4) and the clad layer(3); and forming the 1st-type electrode(5) and the 2nd-type electrode(13).

Abstract translation: 本发明涉及一种使用注射电流的光波导折射率变化的内部全反射型半导体光开关的制造方法。 该方法包括以下步骤：在第1型InP衬底（1）上按顺序升高不掺杂外延法的InGaAsP光波导层（2）和InP包层（3）; 蚀刻要在其上形成光学检测器的包层（3）的某个区域; 通过在盖层（4）的特定区域上升出不掺杂外延法的InGaAsP覆盖层（4）和扩散掺杂剂来形成第二扩散区域; 通过蚀刻覆盖层（4）和覆盖层（3）形成光开关和光检测器的pn结并形成光波导; 并形成第1型电极（5）和第2型电极（13）。

公开(公告)号：KR1019960015270B1

公开(公告)日：1996-11-07

申请号：KR1019920024315

申请日：1992-12-15

Applicant: 한국전자통신연구원

Inventor： 오광룡

IPC: H01L27/146

Abstract: recess etching of a semi-insulating substrate(1) to the height of a photo detector, and growing an n-channel layer(2), an etching barrier layer(3), a p-InGaAs layer(4), an undoped InP layer(5), an undoped absorbing layer(6) and a n-InP layer(7) in sequence; etching the n-InP layer(7) and the absorbing layer(6) and the InP layer(5) selectively except the region of the photo detector; selective etching to separate the photo detector and a transistor electrically; forming p-electrodes(8,9) of the photo detector and the transistor; forming a gate by etching the p-InGaAs layer(4') and the p-InP layer(3') selectively using the p-electrode(9) as a mask; forming two electrodes(10a,10b) of the photo detector and a source electrode(11a) and a drain electrode(11b) of the transistor; etching a polyimide(12) for the contact of a second wiring metal; and connecting the photo detector with the transistor electrically by depositing a wiring metal(13).

Abstract translation: 将半绝缘基板（1）的凹陷蚀刻到光电检测器的高度，并且生长n沟道层（2），蚀刻阻挡层（3），p-InGaAs层（4），未掺杂的InP 层（5），未掺杂的吸收层（6）和n-InP层（7）; 选择性地蚀刻n-InP层（7）和吸收层（6）和InP层（5），除了光电检测器的区域; 选择性蚀刻以将光电检测器和晶体管分离; 形成光检测器和晶体管的p电极（8,9）; 通过使用p电极（9）作为掩模选择性地蚀刻p-InGaAs层（4'）和p-InP层（3'）来形成栅极; 形成光电检测器的两个电极（10a，10b）和晶体管的源电极（11a）和漏电极（11b）; 蚀刻用于第二布线金属的接触的聚酰亚胺（12）; 以及通过沉积布线金属（13）将光电检测器与晶体管电连接。

公开(公告)号：KR1019950010143A

公开(公告)日：1995-04-26

申请号：KR1019930018145

申请日：1993-09-09

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 오광룡 ,  박기성 ,  박종대 ,  김홍만

IPC: H01L29/86 ,  H01L29/8605

Abstract: 본 발명에서 제안된 광스위치는 에피성장, 홈모양의 선택식각, Zn확산, 전극증착 등에 의하여 제작되어지고, 입력광에 대하여 반사면을 이루는 부분에서 홈모양의 식각과 InP와 InGaA의 확산계수의 차이에 의하여 Zn확산이 상대적으로 깊숙이 이루어져 전류주입이 집중되어지구 홈의 양 옆으로는 p/n/p/n 접합이 형성되어 전류주입이 차단되어진다.
즉, p형 옴접촉 면적은 도파로폭 전체에 형성되어져 옴저항은 줄어들고 전류주입은 반사면이 형성된 홈 식각부분으로만 주입된다.

公开(公告)号：KR1019920009898B1

公开(公告)日：1992-11-05

申请号：KR1019890020674

申请日：1989-12-30

Applicant: 한국전자통신연구원

Inventor： 박기성 ,  오광룡 ,  이용탁

IPC: H01L21/82

CPC classification number: H01L27/1443

Abstract: A method for manufacturing the opto-electron integrated circuit integrating the photo-detector and the field effect transistor at one chip comprises: a first epitaxial process growing the channel layer and the photo-absorption layer on the InP substrate; a first etching process for removing the photo- absorption layer after making the etching mask; a second epitaxial process growing the clad layer after removing the photo-sensitive material for etching mask; a process annealing the p- type metal deposited by lift-off method for ohmic contact of the photo-detector and the FET; a second etching process removing the gate part of FET by using the P-type metal as the etching mask.

Abstract translation: 在一个芯片上集成光检测器和场效应晶体管的光电子集成电路的制造方法包括：在InP衬底上生长沟道层和光吸收层的第一外延工艺; 在制作蚀刻掩模之后去除光吸收层的第一蚀刻工艺; 在除去用于蚀刻掩模的光敏材料之后，使包覆层生长的第二外延工艺; 通过剥离法沉积的p-型金属对光检测器和FET的欧姆接触进行退火的工艺; 通过使用P型金属作为蚀刻掩模来去除FET的栅极部分的第二蚀刻工艺。