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公开(公告)号：KR100082489B1
公开(公告)日：1995-02-17
申请号：KR1019910024511
申请日：1991-12-26
Applicant: 한국전자통신연구원
IPC: H01L29/772 , H01L29/778
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公开(公告)号：KR1019940011738B1
公开(公告)日：1994-12-23
申请号：KR1019910024262
申请日：1991-12-24
Applicant: 한국전자통신연구원
IPC: H01L21/28
Abstract: The method includes the steps of depositing and etching lower and upper insulating layers (2)(3) on a semi-insulating cpd. semiconductor substrate (1) to form an ohmic and left-off type opening part, forming a sulfur layer (4) to deposit lower and upper layers (5)(6) thereon, implanting Si ions to mix the semiconducting layer with the ohmic metal layer, and heat-treating to generate the activation of the impurities by the reaction between the metal and semiconductor, after depositing a surface passivation film (8).
Abstract translation: 该方法包括在半绝缘cpd上沉积和蚀刻下绝缘层（2）（3）的步骤。 半导体衬底（1）以形成欧姆和离开型开口部分，形成硫层（4）以沉积其上和下层（5）（6），注入Si离子以将半导体层与欧姆金属 层，并且在沉积表面钝化膜（8）之后通过金属和半导体之间的反应来热处理以产生杂质的活化。
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Patent Agency Ranking
公开(公告)号：KR1019940007592B1
公开(公告)日：1994-08-20
申请号：KR1019910016480
申请日：1991-09-20
IPC: H01L31/00
Abstract: The method is for manufacturing PIN photo diode having high speed operation characteristics. The method comprises the steps of: (A) forming an opto absorbing area on a substreat by LPE of OMVPE method; (B) growing n-INP (33) layer on an opto absorbing layer (31); (C) forming a pattern on the electrode wire bonding area; (D) diffusing P-type intrinsic material on an electrode wire bonding area to form P-N junction structure; (E) forming anti-reflection layer (36) on a n-InP layer (33); (F) etching an area on which electrodes are fomed and (G) forming P-plane electrode in thickness of 0.4 μm by using a lift-off method.
Abstract translation: 该方法用于制造具有高速操作特性的PIN光电二极管。 该方法包括以下步骤：（A）通过OMVPE方法的LPE在子场上形成光吸收区; （B）在光吸收层（31）上生长n-INP（33）层; （C）在电极引线接合区域上形成图案; （D）在电极引线接合区域上扩散P型本征材料以形成P-N结结构; （E）在n-InP层（33）上形成抗反射层（36）; （F）通过剥离法蚀刻电极被覆盖的区域和（G）形成厚度为0.4μm的P面电极。
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公开(公告)号：KR1019930006829A
公开(公告)日：1993-04-22
申请号：KR1019910016479
申请日：1991-09-20
IPC: H01L21/28
Abstract: 본 발명은 고속 PIN포토다이오드를 제조하는 그 제조방법에 있어서, 종래의 PIN포토다이오드의 제조방법은 평면형 INnGaAs/InP 포토다이오드의 구조가 전방 입사형(Front-entry)으로 전극패드가 상당히 큰면적을 차지하고 있기 때문에 커패시턴스를 어느 수중이하로 줄이기가 어렵고, p-InP가 옴접촉특성이 좋지 않으므로 전극형성에 주의하여야 한다. 또는 본딩(전선:wite-bonding)시 충격에 의해 pn접합부의 결정성이 파괴되며 이 경우 상당히 큰 누설전류를 발생하므로 이 충격을 픕수하기 위해 p-면 전극을 배우 두껍게 형성하여야 하고, 이렇게 되면 제조공정이 매우 복잡하게 되는 문제점이 있다.
본 발명은 상기와 같은 문제점을 해결하고자 이루어진 것으로서 p-전극과 n-전극을 동시에 형성하여 고속 PIN 포토다이오드의 제조공정을 간단화하고 이에따라 제조단가의 저렴화를 실현하여 옴접촉특성을 향상시키게 하며, 또 본딩패드를 반절연 InP 기판 위에 형성하여 p-면 전극에 의한 커패시턴스가 발생하지 않도록 커패시턴스를 줄여 주므로써 전극본딩 및 패키징공정이 쉽게 이루어지게 하는 데 그 목적을 둔 것이다.-
公开(公告)号：KR1019920009898B1
公开(公告)日：1992-11-05
申请号：KR1019890020674
申请日：1989-12-30
Applicant: 한국전자통신연구원
IPC: H01L21/82
CPC classification number: H01L27/1443
Abstract: A method for manufacturing the opto-electron integrated circuit integrating the photo-detector and the field effect transistor at one chip comprises: a first epitaxial process growing the channel layer and the photo-absorption layer on the InP substrate; a first etching process for removing the photo- absorption layer after making the etching mask; a second epitaxial process growing the clad layer after removing the photo-sensitive material for etching mask; a process annealing the p- type metal deposited by lift-off method for ohmic contact of the photo-detector and the FET; a second etching process removing the gate part of FET by using the P-type metal as the etching mask.
Abstract translation: 在一个芯片上集成光检测器和场效应晶体管的光电子集成电路的制造方法包括：在InP衬底上生长沟道层和光吸收层的第一外延工艺; 在制作蚀刻掩模之后去除光吸收层的第一蚀刻工艺; 在除去用于蚀刻掩模的光敏材料之后，使包覆层生长的第二外延工艺; 通过剥离法沉积的p-型金属对光检测器和FET的欧姆接触进行退火的工艺; 通过使用P型金属作为蚀刻掩模来去除FET的栅极部分的第二蚀刻工艺。
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公开(公告)号：KR1019950000522B1
公开(公告)日：1995-01-24
申请号：KR1019910021083
申请日：1991-11-25
Applicant: 한국전자통신연구원
IPC: H01L27/06
CPC classification number: H01L21/8252 , H01L27/1443 , H01L31/105 , H01L31/1844 , Y02E10/544 , Y02P70/521
Abstract: The photoelectric integrated device includes a photodetector having an n-InGaAs channel layer (2), an InP etching stop layer (3), an InGaAs absorbing layer (4) and a P-InP layer (5) sequentially formed on the etched semi-insulating substrate (1) and in a mesa structure, and a transistor having an n-InGaAs channel layer (2), an InP etching stop layer (3), and a P-InP layer (5) sequentially formed on the unetched semi-insulating substrate and a P-InGaAs layer (6) formed in a reverse mesa structure on the layer (5), thereby independently maximizing the functions of the photodetector and transistor.
Abstract translation: 光电集成器件包括具有n-InGaAs沟道层（2），InP蚀刻停止层（3），InGaAs吸收层（4）和P-InP层（5）的光电探测器， 绝缘基板（1）和台面结构，以及具有n-InGaAs沟道层（2），InP蚀刻停止层（3）和P-InP层（5）的晶体管，其依次形成在未蚀刻的半导体层 绝缘基板和在层（5）上形成为反台面结构的P-InGaAs层（6），从而独立地使光电检测器和晶体管的功能最大化。
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