公开(公告)号：US20180293011A1

公开(公告)日：2018-10-11

申请号：US15482971

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Prasoonkumar Surti ,  Aravindh V. Anantaraman ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu

IPC: G06F3/06 ,  G06F1/32 ,  G11C11/406

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a memory comprising one or more physical memory chips, and a processor to implement a working set monitor to monitor a working set resident in the one or more physical memory chips. The working set monitor is to adjust a number of the physical memory chips that are powered on based on a size of the working set.

公开(公告)号：US20180286010A1

公开(公告)日：2018-10-04

申请号：US15477018

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Abhishek R. Appu ,  Vasanth Ranganathan

IPC: G06T1/60 ,  G06F12/127 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/123

Abstract: An apparatus to facilitate cache replacement is disclosed. The apparatus includes a cache memory and cache replacement logic to manage data in the cache memory. The cache replacement logic includes tracking logic to track addresses accessed at the cache memory and replacement control logic to monitor the tracking logic and apply a replacement policy based on information received from the tracking logic.

公开(公告)号：US20180284876A1

公开(公告)日：2018-10-04

申请号：US15477009

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Ya-Ti Peng ,  Abhishek R. Appu ,  Wen-Fu Kao ,  Sang-Hee Lee

IPC: G06F1/32 ,  G06F3/01 ,  G06K9/00 ,  H04N7/01 ,  G09G3/20

Abstract: A system of reducing power consumed by a large screen display panel may comprise a display divided into a plurality of segments. A gaze tracker identifies a gaze region where a viewer(s) is looking to increase a refresh rate for segments identified in the gaze region with relation to segments outside of the gaze region. The shading rate of segments outside of the gaze region may also be lowered to save even more power.

公开(公告)号：US10043232B1

公开(公告)日：2018-08-07

申请号：US15482809

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06F9/50 ,  G06F9/48 ,  G06T1/20

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a compute cluster including multiple compute units, a stall notification module to detect that one or more compute units in the compute cluster are stalled and send stall notification, and a rebalance module to receive the stall notification, the rebalance module to migrate a first workload from one or more stalled compute units in response to the stall notification.

公开(公告)号：US20180011711A1

公开(公告)日：2018-01-11

申请号：US15203907

申请日：2016-07-07

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  James A. Valerio ,  Bharath Narasimha Swamy

IPC: G06F9/38 ,  G06F13/16

CPC classification number: G06F9/3887 ,  G06F12/0806 ,  G06F12/084 ,  G06F13/1605 ,  G06F2212/314

Abstract: One embodiment provides for a graphics processor comprising first logic coupled with a first execution unit, the first logic to receive a first single instruction multiple data (SIMD) message from the first execution unit; second logic coupled with a second execution unit, the second logic to receive a second SIMD message from the second execution unit; and third logic coupled with a bank of shared local memory (SLM), the third logic to receive a first request to access the bank of SLM from the first logic, a second request to access the bank of SLM from the second logic, and in a single access cycle, schedule a read access to a read port for the first request and a write access to a write port for the second request.

公开(公告)号：US20180005349A1

公开(公告)日：2018-01-04

申请号：US15201497

申请日：2016-07-03

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Sandeep S. Sodhi ,  Joydeep Ray ,  James A. Valerio

IPC: G06T1/60 ,  G06T1/20 ,  G09G5/00

CPC classification number: G06T1/60 ,  G09G5/39 ,  G09G2360/121 ,  G09G2360/122

Abstract: Methods and apparatus relating to buffering graphics tiled resource translations in a data port controller TLB (Translation Lookaside Buffer) are described. In an embodiment, controller logic causes storage of information corresponding to a tiled resource in a first entry of a Translation Lookaside Buffer (TLB) in response to a request corresponding to the tiled resource. A second entry of the TLB is capable of storing data corresponding to a coherent memory request. The tiled resource comprise data corresponding to a portion of an image. Other embodiments are also disclosed and claimed.

公开(公告)号：US12299766B2

公开(公告)日：2025-05-13

申请号：US17484066

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Prathamesh Raghunath Shinde ,  Ben J. Ashbaugh ,  Wei-Yu Chen ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Dmitry Yurievich Babokin ,  Ankur N. Shah

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06T1/60

Abstract: Systems and methods for supporting generic pointers in hardware of a graphics processing unit (GPU) are provided. In various examples, a GPU includes multiple sub-cores each having a processing resource and a load/store pipeline. The processing resource is operable to receive a memory access message including a pointer and a memory type identifier indicative of the pointer representing a generic pointer. The processing resource is further operable to output a load or store operation to the load/store pipeline based on the memory access message, including computing an address for the load or store operation by adding a base address of a named memory type of a plurality of named memory types referenced by the generic pointer to an offset into a memory of the named memory type. The load/store pipeline is operable to, responsive to receipt of the load or store operation, access the memory at the address.

公开(公告)号：US20250103343A1

公开(公告)日：2025-03-27

申请号：US18955259

申请日：2024-11-21

Applicant: INTEL CORPORATION

Inventor： Christopher J. HUGHES ,  Prasoonkumar SURTI ,  Guei-Yuan LUEH ,  Adam T. LAKE ,  Jill BOYCE ,  Subramaniam MAIYURAN ,  Lidong XU ,  James M. HOLLAND ,  Vasanth RANGANATHAN ,  Nikos KABURLASOS ,  Altug KOKER ,  Abhishek R. Appu

IPC: G06F9/38 ,  G06F9/50 ,  G06F9/54 ,  G06F12/084 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US12242414B2

公开(公告)日：2025-03-04

申请号：US17430963

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Altug Koker ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Joydeep Ray ,  Vasanth Ranganathan

IPC: G06F7/58 ,  G06F7/544 ,  G06F7/575 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

Abstract: Methods and apparatus relating to data initialization techniques. In an example, an apparatus comprises a processor to read one or more metadata codes which map to one or more cache lines in a cache memory and invoke a random number generator to generate random numerical data for the one or more cache lines in response to a determination that the one more metadata codes indicate that the cache lines are to contain random numerical data. Other embodiments are also disclosed and claimed.

公开(公告)号：US12210900B2

公开(公告)日：2025-01-28

申请号：US17746201

申请日：2022-05-17

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Rajkishore Barik ,  Eriko Nurvitadhi ,  Nicolas Galoppo Von Borries ,  Tsung-Han Lin ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan

IPC: G06F9/48 ,  G06T1/20

Abstract: A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.